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Exosphere I2C Driver.
This commit is contained in:
Michael Scire
parent
672d76cb31
commit
c94fe287cb
2 changed files with 273 additions and 0 deletions
203
exosphere/i2c.c
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203
exosphere/i2c.c
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#include <stbool.h>
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#include <stdint.h>
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#include <string.h>
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#include "i2c.h"
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#include "utils.h"
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#include "timers.h"
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/* Prototypes for internal commands. */
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volatile i2c_registers_t *i2c_get_registers_from_id(unsigned int id);
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void i2c_load_config(volatile i2c_registers_t *regs);
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bool i2c_query(unsigned int id, uint8_t device, uint8_t r, void *dst, size_t dst_size);
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bool i2c_send(unsigned int id, uint8_t device, uint8_t r, void *src, size_t src_size);
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bool i2c_write(volatile i2c_registers_t *regs, uint8_t device, void *src, size_t src_size);
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bool i2c_read(volatile i2c_registers_t *regs, uint8_t device, void *dst, size_t dst_size);
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/* Initialize I2C based on registers. */
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void i2c_init(unsigned int id) {
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volatile i2c_registers_t *regs = i2c_get_registers_from_id(id);
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/* Setup divisor, and clear the bus. */
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regs->I2C_I2C_CLK_DIVISOR_REGISTER_0 = 0x50001;
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regs->I2C_I2C_BUS_CLEAR_CONFIG_0 = 0x90003;
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/* Load hardware configuration. */
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i2c_load_config(regs);
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/* Wait a while until BUS_CLEAR_DONE is set. */
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for (unsigned int i = 0; i < 10; i++) {
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wait(20000);
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if (regs->I2C_INTERRUPT_STATUS_REGISTER_0 & 0x800) {
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break;
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}
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}
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/* Read the BUS_CLEAR_STATUS. Result doesn't matter. */
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regs->I2C_I2C_BUS_CLEAR_STATUS_0;
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/* Read and set the Interrupt Status. */
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uint32_t int_status = regs->I2C_INTERRUPT_STATUS_REGISTER_0;
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regs->I2C_INTERRUPT_STATUS_REGISTER_0 = int_status;
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}
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/* Sets a bit in a PMIC register over I2C during CPU shutdown. */
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void i2c_send_pmic_cpu_shutdown_cmd(void) {
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uint32_t val = 0;
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/* PMIC == Device 4:3C. */
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i2c_query(4, 0x3C, 0x41, &val, 1);
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val |= 4;
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i2c_send(4, 0x3C, 0x41, &val, 1);
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}
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/* Queries the value of TI charger bit over I2C. */
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bool i2c_query_ti_charger_bit_7(void) {
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uint32_t val = 0;
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/* TI Charger = Device 0:6B. */
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i2c_query(0, 0x6B, 0, &val, 1);
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return (val & 0x80) != 0;
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}
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/* Clears TI charger bit over I2C. */
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void i2c_clear_ti_charger_bit_7(void) {
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uint32_t val = 0;
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/* TI Charger = Device 0:6B. */
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i2c_query(0, 0x6B, 0, &val, 1);
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val &= 0x7F;
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i2c_send(0, 0x6B, 0, &val, 1);
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}
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/* Sets TI charger bit over I2C. */
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void i2c_set_ti_charger_bit_7(void) {
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uint32_t val = 0;
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/* TI Charger = Device 0:6B. */
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i2c_query(0, 0x6B, 0, &val, 1);
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val |= 0x80;
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i2c_send(0, 0x6B, 0, &val, 1);
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}
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/* Get registers pointer based on I2C ID. */
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volatile i2c_registers_t *i2c_get_registers_from_id(unsigned int id) {
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switch (id) {
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case 0:
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return I2C1_REGS;
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case 1:
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return I2C2_REGS;
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case 2:
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return I2C3_REGS;
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case 3:
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return I2C4_REGS;
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case 4:
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return I2C5_REGS;
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case 5:
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return I2C6_REGS;
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default:
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panic();
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}
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return NULL;
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}
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/* Load hardware config for I2C4. */
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void i2c_load_config(volatile i2c_registers_t *regs) {
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/* Set MSTR_CONFIG_LOAD, TIMEOUT_CONFIG_LOAD, undocumented bit. */
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regs->I2C_I2C_CONFIG_LOAD_0 = 0x25;
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/* Wait a bit for master config to be loaded. */
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for (unsigned int i = 0; i < 20; i++) {
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wait(1);
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if (!(regs->I2C_I2C_CONFIG_LOAD_0 & 1)) {
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break;
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}
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}
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}
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/* Reads a register from a device over I2C, writes result to output. */
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bool i2c_query(unsigned int id, uint8_t device, uint8_t r, void *dst, size_t dst_size) {
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volatile i2c_registers_t *regs = i2c_get_registers_from_id(id);
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uint32_t val = r;
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/* Write single byte register ID to device. */
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if (!i2c_write(regs, device, &val, 1)) {
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return false;
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}
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/* Limit output size to 32-bits. */
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if (dst_size > 4) {
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return false;
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}
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return i2c_read(regs, device, dst, dst_size);
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}
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/* Writes a value to a register over I2C. */
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bool i2c_send(unsigned int id, uint8_t device, uint8_t r, void *src, size_t src_size) {
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uint32_t val = r;
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if (src_size <= 3) {
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memcpy(((uint8_t *)&val) + 1, src, src_size);
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return i2c_write(i2c_get_registers_from_id(id), &val, src_size + 1, device);
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} else {
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return false;
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}
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}
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/* Writes bytes to device over I2C. */
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bool i2c_write(volatile i2c_registers_t *regs, uint8_t device, void *src, size_t src_size) {
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if (src_size > 4) {
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return false;
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}
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/* Set device for 7-bit write mode. */
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regs->I2C_I2C_CMD_ADDR0_0 = device << 1;
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/* Load in data to write. */
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regs->I2C_I2C_CMD_DATA1_0 = read32le(src, 0);
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/* Set config with LENGTH = src_size, NEW_MASTER_FSM, DEBOUNCE_CNT = 4T. */
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regs->I2C_I2C_CNFG_0 = ((src_size << 1) - 2) | 0x2800;
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i2c_load_config(regs);
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/* Config |= SEND; */
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regs->I2C_I2C_CNFG_0 |= 0x200;
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while (regs->I2C_I2C_STATUS_0 & 0x100) {
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/* Wait until not busy. */
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}
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/* Return CMD1_STAT == SL1_XFER_SUCCESSFUL. */
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return (regs->I2C_I2C_STATUS_0 & 0xF) == 0;
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}
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/* Reads bytes from device over I2C. */
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bool i2c_read(volatile i2c_registers_t *regs, uint8_t device, void *dst, size_t dst_size) {
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if (dst_size > 4) {
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return false;
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}
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/* Set device for 7-bit read mode. */
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regs->I2C_I2C_CMD_ADDR0_0 = (device << 1) | 1;
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/* Set config with LENGTH = dst_size, NEW_MASTER_FSM, DEBOUNCE_CNT = 4T. */
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regs->I2C_I2C_CNFG_0 = ((dst_size << 1) - 2) | 0x2840;
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i2c_load_config(regs);
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/* Config |= SEND; */
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regs->I2C_I2C_CNFG_0 |= 0x200;
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while (regs->I2C_I2C_STATUS_0 & 0x100) {
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/* Wait until not busy. */
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}
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/* Ensure success. */
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if ((regs->I2C_I2C_STATUS_0 & 0xF) != 0) {
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return false;
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}
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uint32_t val = regs->I2C_I2C_CMD_DATA1_0;
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memcpy(dst, &val, dst_size);
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return true;
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}
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70
exosphere/i2c.h
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70
exosphere/i2c.h
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#ifndef EXOSPHERE_I2C_H
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#define EXOSPHERE_I2C_H
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#include <stdbool.h>
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#include <stdint.h>
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#include "mmu.h"
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/* Exosphere driver for the Tegra X1 I2C registers. */
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typedef struct {
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uint32_t I2C_I2C_CNFG_0;
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uint32_t I2C_I2C_CMD_ADDR0_0;
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uint32_t I2C_I2C_CMD_ADDR1_0;
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uint32_t I2C_I2C_CMD_DATA1_0;
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uint32_t I2C_I2C_CMD_DATA2_0;
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uint32_t _0x14;
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uint32_t _0x18;
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uint32_t I2C_I2C_STATUS_0;
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uint32_t I2C_I2C_SL_CNFG_0;
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uint32_t I2C_I2C_SL_RCVD_0;
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uint32_t I2C_I2C_SL_STATUS_0;
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uint32_t I2C_I2C_SL_ADDR1_0;
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uint32_t I2C_I2C_SL_ADDR2_0;
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uint32_t I2C_I2C_TLOW_SEXT_0;
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uint32_t _0x38;
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uint32_t I2C_I2C_SL_DELAY_COUNT_0;
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uint32_t I2C_I2C_SL_INT_MASK_0;
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uint32_t I2C_I2C_SL_INT_SOURCE_0;
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uint32_t I2C_I2C_SL_INT_SET_0;
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uint32_t _0x4C;
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uint32_t I2C_I2C_TX_PACKET_FIFO_0;
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uint32_t I2C_I2C_RX_FIFO_0;
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uint32_t I2C_PACKET_TRANSFER_STATUS_0;
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uint32_t I2C_FIFO_CONTROL_0;
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uint32_t I2C_FIFO_STATUS_0;
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uint32_t I2C_INTERRUPT_MASK_REGISTER_0;
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uint32_t I2C_INTERRUPT_STATUS_REGISTER_0;
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uint32_t I2C_I2C_CLK_DIVISOR_REGISTER_0;
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uint32_t I2C_I2C_INTERRUPT_SOURCE_REGISTER_0;
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uint32_t I2C_I2C_INTERRUPT_SET_REGISTER_0;
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uint32_t I2C_I2C_SLV_TX_PACKET_FIFO_0;
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uint32_t I2C_I2C_SLV_RX_FIFO_0;
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uint32_t I2C_I2C_SLV_PACKET_STATUS_0;
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uint32_t I2C_I2C_BUS_CLEAR_CONFIG_0;
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uint32_t I2C_I2C_BUS_CLEAR_STATUS_0;
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uint32_t I2C_I2C_CONFIG_LOAD_0;
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uint32_t _0x90;
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uint32_t I2C_I2C_INTERFACE_TIMING_0_0;
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uint32_t I2C_I2C_INTERFACE_TIMING_1_0;
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uint32_t I2C_I2C_HS_INTERFACE_TIMING_0_0;
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uint32_t I2C_I2C_HS_INTERFACE_TIMING_1_0;
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} i2c_registers_t;
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#define I2C1_REGS ((volatile i2c_registers_t *)(mmio_get_device_address(MMIO_DEVID_DTV_I2C234) + 0x000))
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#define I2C2_REGS ((volatile i2c_registers_t *)(mmio_get_device_address(MMIO_DEVID_DTV_I2C234) + 0x400))
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#define I2C3_REGS ((volatile i2c_registers_t *)(mmio_get_device_address(MMIO_DEVID_DTV_I2C234) + 0x500))
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#define I2C4_REGS ((volatile i2c_registers_t *)(mmio_get_device_address(MMIO_DEVID_DTV_I2C234) + 0x700))
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#define I2C5_REGS ((volatile i2c_registers_t *)(mmio_get_device_address(MMIO_DEVID_I2C56_SPI2B) + 0x000))
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#define I2C6_REGS ((volatile i2c_registers_t *)(mmio_get_device_address(MMIO_DEVID_I2C56_SPI2B) + 0x100))
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void i2c_init(unsigned int id);
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void i2c_send_pmic_cpu_shutdown_cmd(void);
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bool i2c_query_ti_charger_bit_7(void);
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void i2c_clear_ti_charger_bit_7(void);
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void i2c_set_ti_charger_bit_7(void);
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#endif
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