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Code Issues Releases Activity

warmboot: fix bugs in firmware

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This commit is contained in:
Michael Scire 2019-01-20 02:37:04 -08:00
parent add52b90c9
commit caba025e97
4 changed files with 9 additions and 9 deletions
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4
exosphere/lp0fw/src/cluster.c
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@ -37,7 +37,7 @@ static void cluster_pmc_enable_partition(uint32_t mask, uint32_t toggle) {
/* Remove clamping. */ /* Remove clamping. */
APBDEV_PMC_REMOVE_CLAMPING_CMD_0 = mask; APBDEV_PMC_REMOVE_CLAMPING_CMD_0 = mask;
while (!(APBDEV_PMC_CLAMP_STATUS_0 & mask)) { } while (APBDEV_PMC_CLAMP_STATUS_0 & mask) { }
} }
void cluster_initialize_cpu(void) { void cluster_initialize_cpu(void) {
@ -113,7 +113,7 @@ void cluster_initialize_cpu(void) {
/* Remove SW clamp to CRAIL. */ /* Remove SW clamp to CRAIL. */
APBDEV_PMC_SET_SW_CLAMP_0 = 0; APBDEV_PMC_SET_SW_CLAMP_0 = 0;
APBDEV_PMC_REMOVE_CLAMPING_CMD_0 = 1; APBDEV_PMC_REMOVE_CLAMPING_CMD_0 = 1;
while (!(APBDEV_PMC_CLAMP_STATUS_0 & 1)) { } while (APBDEV_PMC_CLAMP_STATUS_0 & 1) { }
/* Nintendo manually counts down from 8. I am not sure why this happens. */ /* Nintendo manually counts down from 8. I am not sure why this happens. */
{ {

4
exosphere/lp0fw/src/i2c.c
View file

@ -27,8 +27,8 @@ void i2c_set_test_master_config_load(void) {
/* Set MSTR_CONFIG_LOAD. */ /* Set MSTR_CONFIG_LOAD. */
I2C_I2C_CONFIG_LOAD_0 = 0x1; I2C_I2C_CONFIG_LOAD_0 = 0x1;
while (!(I2C_I2C_CONFIG_LOAD_0 & 1)) { while (I2C_I2C_CONFIG_LOAD_0 & 1) {
/* Wait forever until it's set. */ /* Wait forever until it's unset. */
} }
} }

2
exosphere/lp0fw/src/misc.c
View file

@ -48,5 +48,5 @@ void misc_configure_device_dbg_settings(void) {
void misc_restore_ram_svop(void) { void misc_restore_ram_svop(void) {
/* This sets CFG2TMC_RAM_SVOP_PDP to 0x2. */ /* This sets CFG2TMC_RAM_SVOP_PDP to 0x2. */
APB_MISC_GP_ASDBGREG_0 |= 0x02000000; APB_MISC_GP_ASDBGREG_0 = (APB_MISC_GP_ASDBGREG_0 & 0xFCFFFFFF) | 0x02000000;
} }

8
exosphere/lp0fw/src/pmc.h
View file

@ -51,10 +51,10 @@
#define APBDEV_PMC_SECURE_SCRATCH34_0 MAKE_PMC_REG(0x368) #define APBDEV_PMC_SECURE_SCRATCH34_0 MAKE_PMC_REG(0x368)
#define APBDEV_PMC_SECURE_SCRATCH35_0 MAKE_PMC_REG(0x36C) #define APBDEV_PMC_SECURE_SCRATCH35_0 MAKE_PMC_REG(0x36C)
#define APBDEV_PMC_SECURE_SCRATCH112_0 MAKE_PMC_REG(0x718) #define APBDEV_PMC_SECURE_SCRATCH112_0 MAKE_PMC_REG(0xB18)
#define APBDEV_PMC_SECURE_SCRATCH113_0 MAKE_PMC_REG(0x71C) #define APBDEV_PMC_SECURE_SCRATCH113_0 MAKE_PMC_REG(0xB1C)
#define APBDEV_PMC_SECURE_SCRATCH114_0 MAKE_PMC_REG(0x720) #define APBDEV_PMC_SECURE_SCRATCH114_0 MAKE_PMC_REG(0xB20)
#define APBDEV_PMC_SECURE_SCRATCH115_0 MAKE_PMC_REG(0x724) #define APBDEV_PMC_SECURE_SCRATCH115_0 MAKE_PMC_REG(0xB24)
#define APBDEV_PMC_IO_DPD3_REQ_0 MAKE_PMC_REG(0x45C) #define APBDEV_PMC_IO_DPD3_REQ_0 MAKE_PMC_REG(0x45C)
#define APBDEV_PMC_IO_DPD3_STATUS_0 MAKE_PMC_REG(0x460) #define APBDEV_PMC_IO_DPD3_STATUS_0 MAKE_PMC_REG(0x460)