mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-11-22 20:06:40 +00:00
fusee: fix sleep/wake on 6.x
This commit is contained in:
Michael Scire
SciresM
parent
bb11c57e7d
commit
cd62d83586
3 changed files with 48 additions and 37 deletions
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@ -13,7 +13,7 @@
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef FUSEE_CAR_H
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#define FUSEE_CAR_H
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@ -37,23 +37,27 @@
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/* Clock and reset devices. */
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typedef enum {
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CARDEVICE_UARTA = ((0 << 5) | 0x6),
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CARDEVICE_UARTB = ((0 << 5) | 0x7),
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CARDEVICE_UARTC = ((1 << 5) | 0x17),
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CARDEVICE_I2C1 = ((0 << 5) | 0xC),
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CARDEVICE_I2C5 = ((1 << 5) | 0xF),
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CARDEVICE_TZRAM = ((3 << 5) | 0x1E),
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CARDEVICE_SE = ((3 << 5) | 0x1F),
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CARDEVICE_HOST1X = ((0 << 5) | 0x1C),
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CARDEVICE_TSEC = ((2 << 5) | 0x13),
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CARDEVICE_SOR_SAFE = ((6 << 5) | 0x1E),
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CARDEVICE_SOR0 = ((5 << 5) | 0x16),
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CARDEVICE_SOR1 = ((5 << 5) | 0x17),
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CARDEVICE_KFUSE = ((1 << 5) | 0x8),
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CARDEVICE_CL_DVFS = ((4 << 5) | 0x1B),
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CARDEVICE_BPMP = ((0 << 5) | 0x1),
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CARDEVICE_UARTA = ((0 << 5) | 0x6),
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CARDEVICE_UARTB = ((0 << 5) | 0x7),
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CARDEVICE_I2C1 = ((0 << 5) | 0xC),
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CARDEVICE_USBD = ((0 << 5) | 0x16),
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CARDEVICE_HOST1X = ((0 << 5) | 0x1C),
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CARDEVICE_AHBDMA = ((1 << 5) | 0x1),
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CARDEVICE_APBDMA = ((1 << 5) | 0x2),
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CARDEVICE_KFUSE = ((1 << 5) | 0x8),
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CARDEVICE_I2C5 = ((1 << 5) | 0xF),
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CARDEVICE_UARTC = ((1 << 5) | 0x17),
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CARDEVICE_USB2 = ((1 << 5) | 0x1A),
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CARDEVICE_CORESIGHT = ((2 << 5) | 0x9),
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CARDEVICE_ACTMON = ((3 << 5) | 0x17),
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CARDEVICE_BPMP = ((0 << 5) | 0x1)
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CARDEVICE_TSEC = ((2 << 5) | 0x13),
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CARDEVICE_ACTMON = ((3 << 5) | 0x17),
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CARDEVICE_TZRAM = ((3 << 5) | 0x1E),
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CARDEVICE_SE = ((3 << 5) | 0x1F),
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CARDEVICE_CL_DVFS = ((4 << 5) | 0x1B),
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CARDEVICE_SOR0 = ((5 << 5) | 0x16),
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CARDEVICE_SOR1 = ((5 << 5) | 0x17),
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CARDEVICE_SOR_SAFE = ((6 << 5) | 0x1E),
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} CarDevice;
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/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
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@ -97,31 +101,31 @@ typedef struct {
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uint32_t pllc_out;
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uint32_t pllc_misc0;
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uint32_t pllc_misc1;
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/* PLLM 0x90-0x9c */
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uint32_t pllm_base;
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uint32_t pllm_out;
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uint32_t pllm_misc1;
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uint32_t pllm_misc2;
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/* PLLP 0xa0-0xac */
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uint32_t pllp_base;
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uint32_t pllp_outa;
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uint32_t pllp_outb;
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uint32_t pllp_misc;
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/* PLLA 0xb0-0xbc */
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uint32_t plla_base;
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uint32_t plla_out;
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uint32_t plla_misc0;
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uint32_t plla_misc1;
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/* PLLU 0xc0-0xcc */
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uint32_t pllu_base;
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uint32_t pllu_out;
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uint32_t pllu_misc1;
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uint32_t pllu_misc2;
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/* PLLD 0xd0-0xdc */
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uint32_t plld_base;
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uint32_t plld_out;
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@ -131,13 +135,13 @@ typedef struct {
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/* PLLX 0xe0-0xe4 */
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uint32_t pllx_base;
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uint32_t pllx_misc;
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/* PLLE 0xe8-0xf4 */
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uint32_t plle_base;
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uint32_t plle_misc;
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uint32_t plle_ss_cntl1;
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uint32_t plle_ss_cntl2;
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uint32_t lvl2_clk_gate_ovra; /* _LVL2_CLK_GATE_OVRA_0, 0xf8 */
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uint32_t lvl2_clk_gate_ovrb; /* _LVL2_CLK_GATE_OVRB_0, 0xfc */
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@ -188,7 +192,7 @@ typedef struct {
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uint32_t _0x1e0[5];
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uint32_t clk_source_tsec; /* _CLK_SOURCE_TSEC_0, 0x1f4 */
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uint32_t _0x1f8;
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uint32_t clk_spare2; /* _CLK_SPARE2_0, 0x1fc */
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uint32_t _0x200[32];
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@ -257,7 +261,7 @@ typedef struct {
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uint32_t lvl2_clk_gate_ovrc; /* _LVL2_CLK_GATE_OVRC, 0x3a0 */
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uint32_t lvl2_clk_gate_ovrd; /* _LVL2_CLK_GATE_OVRD, 0x3a4 */
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uint32_t _0x3a8[2];
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uint32_t _0x3b0;
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uint32_t clk_source_mselect; /* _CLK_SOURCE_MSELECT_0, 0x3b4 */
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uint32_t clk_source_tsensor; /* _CLK_SOURCE_TSENSOR_0, 0x3b8 */
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@ -371,13 +375,13 @@ typedef struct {
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uint32_t spare_reg0; /* _SPARE_REG0_0, 0x55c */
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uint32_t audio_sync_clk_dmic1; /* _AUDIO_SYNC_CLK_DMIC1_0, 0x560 */
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uint32_t audio_sync_clk_dmic2; /* _AUDIO_SYNC_CLK_DMIC2_0, 0x564 */
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uint32_t _0x568[2];
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uint32_t plld2_ss_cfg; /* _PLLD2_SS_CFG, 0x570 */
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uint32_t plld2_ss_ctrl1; /* _PLLD2_SS_CTRL1_0, 0x574 */
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uint32_t plld2_ss_ctrl2; /* _PLLD2_SS_CTRL2_0, 0x578 */
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uint32_t _0x57c[5];
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uint32_t plldp_base; /* _PLLDP_BASE, 0x590*/
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uint32_t plldp_misc; /* _PLLDP_MISC, 0x594 */
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uint32_t plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */
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@ -399,7 +403,7 @@ typedef struct {
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uint32_t pllx_misc4; /* _PLLX_MISC_4_0, 0x5f0 */
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uint32_t pllx_misc5; /* _PLLX_MISC_5_0, 0x5f4 */
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uint32_t _0x5f8[2];
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uint32_t clk_source_xusb_core_host; /* _CLK_SOURCE_XUSB_CORE_HOST_0, 0x600 */
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uint32_t clk_source_xusb_falcon; /* _CLK_SOURCE_XUSB_FALCON_0, 0x604 */
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uint32_t clk_source_xusb_fs; /* _CLK_SOURCE_XUSB_FS_0, 0x608 */
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@ -428,7 +432,7 @@ typedef struct {
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uint32_t clk_source_uart_fst_mipi_cal; /* _CLK_SOURCE_UART_FST_MIPI_CAL_0, 0x66c */
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uint32_t _0x670[2];
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uint32_t clk_source_vic; /* _CLK_SOURCE_VIC_0, 0x678 */
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uint32_t pllp_outc; /* _PLLP_OUTC_0, 0x67c */
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uint32_t pllp_misc1; /* _PLLP_MISC1_0, 0x680 */
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uint32_t _0x684[2];
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@ -439,14 +443,14 @@ typedef struct {
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uint32_t clk_source_nvdec; /* _CLK_SOURCE_NVDEC_0, 0x698 */
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uint32_t clk_source_nvjpg; /* _CLK_SOURCE_NVJPG_0, 0x69c */
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uint32_t clk_source_nvenc; /* _CLK_SOURCE_NVENC_0, 0x6a0 */
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uint32_t plla1_base; /* _PLLA1_BASE_0, 0x6a4 */
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uint32_t plla1_misc0; /* _PLLA1_MISC_0_0, 0x6a8 */
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uint32_t plla1_misc1; /* _PLLA1_MISC_1_0, 0x6ac */
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uint32_t plla1_misc2; /* _PLLA1_MISC_2_0, 0x6b0 */
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uint32_t plla1_misc3; /* _PLLA1_MISC_3_0, 0x6b4 */
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uint32_t audio_sync_clk_dmic3; /* _AUDIO_SYNC_CLK_DMIC3_0, 0x6b8 */
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uint32_t clk_source_dmic3; /* _CLK_SOURCE_DMIC3_0, 0x6bc */
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uint32_t clk_source_ape; /* _CLK_SOURCE_APE_0, 0x6c0 */
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uint32_t clk_source_qspi; /* _CLK_SOURCE_QSPI_0, 0x6c4 */
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@ -455,11 +459,11 @@ typedef struct {
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uint32_t clk_source_pex_sata_usb_rx_byp; /* _CLK_SOURCE_PEX_SATA_USB_RX_BYP_0, 0x6d0 */
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uint32_t clk_source_maud; /* _CLK_SOURCE_MAUD_0, 0x6d4 */
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uint32_t clk_source_tsecb; /* _CLK_SOURCE_TSECB_0, 0x6d8 */
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uint32_t clk_cpug_misc1; /* _CLK_CPUG_MISC1_0, 0x6dc */
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uint32_t aclk_burst_policy; /* _ACLK_BURST_POLICY_0, 0x6e0 */
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uint32_t super_aclk_divider; /* _SUPER_ACLK_DIVIDER_0, 0x6e4 */
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uint32_t nvenc_super_clk_divider; /* _NVENC_SUPER_CLK_DIVIDER_0, 0x6e8 */
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uint32_t vi_super_clk_divider; /* _VI_SUPER_CLK_DIVIDER_0, 0x6ec */
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uint32_t vic_super_clk_divider; /* _VIC_SUPER_CLK_DIVIDER_0, 0x6f0 */
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@ -470,7 +474,7 @@ typedef struct {
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uint32_t se_super_clk_divider; /* _SE_SUPER_CLK_DIVIDER_0, 0x704 */
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uint32_t tsec_super_clk_divider; /* _TSEC_SUPER_CLK_DIVIDER_0, 0x708 */
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uint32_t tsecb_super_clk_divider; /* _TSECB_SUPER_CLK_DIVIDER_0, 0x70c */
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uint32_t clk_source_uartape; /* _CLK_SOURCE_UARTAPE_0, 0x710 */
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uint32_t clk_cpug_misc2; /* _CLK_CPUG_MISC2_0, 0x714 */
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uint32_t clk_source_dbgapb; /* _CLK_SOURCE_DBGAPB_0, 0x718 */
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@ -484,7 +488,7 @@ typedef struct {
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uint32_t sdmmc4_pllc4_out0_shaper_ctrl; /* _SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0, 0x738 */
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uint32_t sdmmc4_pllc4_out1_shaper_ctrl; /* _SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0, 0x73c */
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uint32_t sdmmc4_pllc4_out2_shaper_ctrl; /* _SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0, 0x740 */
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uint32_t sdmmc4_div_clk_shaper_ctrl; /* _SDMMC4_DIV_CLK_SHAPER_CTRL_0, 0x744 */
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uint32_t sdmmc4_div_clk_shaper_ctrl; /* _SDMMC4_DIV_CLK_SHAPER_CTRL_0, 0x744 */
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} tegra_car_t;
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static inline volatile tegra_car_t *car_get_regs(void) {
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@ -24,6 +24,7 @@
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#include "nxboot.h"
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#include "nxfs.h"
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#include "bct.h"
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#include "car.h"
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#include "di.h"
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#include "mc.h"
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#include "se.h"
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@ -1015,6 +1016,12 @@ uint32_t nxboot_main(void) {
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/* Wait for the splash screen to have been displayed for as long as it should be. */
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splash_screen_wait_delay();
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/* Set reset for USBD, USB2, AHBDMA, and APBDMA. */
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rst_enable(CARDEVICE_USBD);
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rst_enable(CARDEVICE_USB2);
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rst_enable(CARDEVICE_AHBDMA);
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rst_enable(CARDEVICE_APBDMA);
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/* Return the memory address for booting CPU0. */
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return (uint32_t)exosphere_memaddr;
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}
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@ -203,12 +203,12 @@ DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_NONCPURESET, 29, DISABLE, ENA
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HANDLER(H, MEM, 1, 0) \
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HANDLER(H, AHBDMA, 1, 1) \
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HANDLER(H, APBDMA, 1, 2) \
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HANDLER(H, USB2, 1, 26) \
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HANDLER(H, PMC, 1, 6) \
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HANDLER(H, FUSE, 1, 7) \
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HANDLER(H, KFUSE, 1, 8) \
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HANDLER(H, I2C5, 1, 15) \
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HANDLER(H, EMC, 1, 25) \
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HANDLER(H, USB2, 1, 26) \
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HANDLER(U, CSITE, 2, 9) \
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HANDLER(U, IRAMA, 2, 20) \
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HANDLER(U, IRAMB, 2, 21) \
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