diff --git a/thermosphere/src/irq.c b/thermosphere/src/irq.c
index e7dc8c02d..fa4127a0b 100644
--- a/thermosphere/src/irq.c
+++ b/thermosphere/src/irq.c
@@ -181,7 +181,6 @@ void handleIrqException(ExceptionStackFrame *frame, bool isLowerEl, bool isA32)
         // Deactivate the interrupt
         gicc->dir = iar;
     } else {
-        if (irqId == 30) g_irqManager.gic.gicd->ispendr[0x80/32] = 0xFFFFFFFF;
         vgicEnqueuePhysicalIrq(irqId);
     }
 
diff --git a/thermosphere/src/sysreg_traps.c b/thermosphere/src/sysreg_traps.c
index a4992e184..64510a516 100644
--- a/thermosphere/src/sysreg_traps.c
+++ b/thermosphere/src/sysreg_traps.c
@@ -68,32 +68,14 @@ void doSystemRegisterWrite(ExceptionStackFrame *frame, u32 iss, u32 reg)
 
     val = readFrameRegisterZ(frame, reg);
 
-    bool reevalSoftwareBreakpoints = false;
-
     // Hooks go here:
     switch (iss) {
-        case ENCODE_SYSREG_ISS(TTBR0_EL1):
-        case ENCODE_SYSREG_ISS(TTBR1_EL1):
-        case ENCODE_SYSREG_ISS(TCR_EL1):
-        case ENCODE_SYSREG_ISS(SCTLR_EL1):
-            reevalSoftwareBreakpoints = true;
-            break;
         default:
             break;
     }
 
-    if (reevalSoftwareBreakpoints) {
-        revertAllSoftwareBreakpoints();
-    }
-
     doSystemRegisterRwImpl(&val, iss);
 
-    if (reevalSoftwareBreakpoints) {
-        __dsb_sy();
-        __isb();
-        applyAllSoftwareBreakpoints();
-    }
-
     skipFaultingInstruction(frame, 4);
 }
 
diff --git a/thermosphere/src/traps.c b/thermosphere/src/traps.c
index b552b513c..9b015cb64 100644
--- a/thermosphere/src/traps.c
+++ b/thermosphere/src/traps.c
@@ -34,9 +34,6 @@ void enableTraps(void)
 {
     u64 hcr = GET_SYSREG(hcr_el2);
 
-    // Trap memory-related sysreg writes (note: not supported by QEMU yet)
-    hcr |= HCR_TVM;
-
     // Trap SMC instructions
     hcr |= HCR_TSC;