mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-12-23 02:42:09 +00:00
fusee_cpp: implement erista pll selection logic for mtc
This commit is contained in:
parent
d2f3b806d6
commit
d7192343d8
4 changed files with 207 additions and 1 deletions
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@ -22,6 +22,10 @@ namespace ams::nxboot {
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namespace {
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constexpr inline const uintptr_t CLKRST = secmon::MemoryRegionPhysicalDeviceClkRst.GetAddress();
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static constinit bool g_next_pll = false;
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#include "fusee_mtc_tables_erista.inc"
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using EmcDvfsTimingTable = erista::EmcDvfsTimingTable;
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@ -41,6 +45,171 @@ namespace ams::nxboot {
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}
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}
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bool IsSamePll(u32 next_2x, u32 prev_2x) {
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if (next_2x == prev_2x) {
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return true;
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} else if ((next_2x == PLLM_OUT0 || next_2x == PLLM_UD) && (prev_2x == PLLM_OUT0 || prev_2x == PLLM_UD)) {
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return true;
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} else {
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return false;
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}
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}
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bool PllReprogram(u32 next_rate_khz, u32 next_clk_src, u32 prev_rate_khz, u32 prev_clk_src) {
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/* Get current pll/divp value. */
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u32 pll_base, pll_p;
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switch (reg::GetValue(CLKRST + CLK_RST_CONTROLLER_CLK_SOURCE_EMC, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC))) {
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case PLLM_UD:
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case PLLM_OUT0:
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pll_base = reg::Read(CLKRST + CLK_RST_CONTROLLER_PLLM_BASE);
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pll_p = reg::GetField(pll_base, CLK_RST_REG_BITS_MASK(PLLM_BASE_PLLM_DIVP));
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break;
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case PLLMB_UD:
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case PLLMB_OUT0:
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pll_base = reg::Read(CLKRST + CLK_RST_CONTROLLER_PLLMB_BASE);
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pll_p = reg::GetField(pll_base, CLK_RST_REG_BITS_MASK(PLLMB_BASE_PLLMB_DIVP));
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break;
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default:
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pll_base = 0;
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pll_p = 0;
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}
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/* Check pll divp. */
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if (pll_p > 5) {
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ShowFatalError("Invalid PLL divp: %" PRIu32 "\n", pll_p);
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}
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/* Get clk src/divisor. */
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const u32 next_2x = reg::GetField(next_clk_src, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC));
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const u32 prev_2x = reg::GetField(prev_clk_src, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC));
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u32 next_div = reg::GetField(next_clk_src, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR));
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u32 prev_div = reg::GetField(prev_clk_src, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR));
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/* Update divisor, if necessary. */
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if (next_2x == PLLM_UD || next_2x == PLLMB_UD) {
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next_div = 0;
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}
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if (prev_2x == PLLM_UD || prev_2x == PLLMB_UD) {
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prev_div = 0;
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}
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/* If the pll is different, reprogramming is necessary. */
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if (!IsSamePll(next_2x, prev_2x)) {
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return true;
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}
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/* Return whether the ratios are different. */
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const float next_freq = next_rate_khz * (1 + (next_div >> 1) + (0.5 * (next_div & 1))) * (pll_p + 1);
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const float prev_freq = prev_rate_khz * (1 + (prev_div >> 1) + (0.5 * (prev_div & 1))) * (pll_p + 1);
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const float ratio = prev_freq / next_freq;
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return ratio > 1.01 || ratio < 0.99;
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}
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u32 ProgramPllm(u32 next_rate_khz, u32 next_clk_src, bool is_pllmb) {
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/* Hardcode values for 1600MHz. */
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if (next_rate_khz != 1600000) {
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ShowFatalError("Unexpected ProgramPllm next rate %" PRIu32 "\n", next_rate_khz);
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}
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const u32 divn = 0x7D;
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const u32 divm = 0x03;
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const u32 divp = 0x00;
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const auto next_2x = reg::GetField(next_clk_src, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC));
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if (is_pllmb) {
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/* Set divisors. */
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reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLMB_BASE, CLK_RST_REG_BITS_VALUE(PLLMB_BASE_PLLMB_DIVM, divm),
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CLK_RST_REG_BITS_VALUE(PLLMB_BASE_PLLMB_DIVN, divn),
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CLK_RST_REG_BITS_VALUE(PLLMB_BASE_PLLMB_DIVP, divp));
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reg::Read(CLKRST + CLK_RST_CONTROLLER_PLLMB_BASE);
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/* Set enable. */
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reg::ReadWrite(CLKRST + CLK_RST_CONTROLLER_PLLMB_BASE, CLK_RST_REG_BITS_ENUM(PLLMB_BASE_PLLMB_ENABLE, ENABLE));
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/* Adjust next clock source. */
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if (next_2x == PLLM_UD) {
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reg::SetField(next_clk_src, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, PLLMB_UD));
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} else if (next_2x == PLLM_OUT0) {
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reg::SetField(next_clk_src, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, PLLMB_OUT0));
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}
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/* Wait for pll to lock. */
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while (!reg::HasValue(CLKRST + CLK_RST_CONTROLLER_PLLMB_BASE, CLK_RST_REG_BITS_ENUM(PLLMB_BASE_PLLMB_LOCK, LOCK))) {
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/* ... */
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}
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} else {
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/* Set divisors. */
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reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLM_BASE, CLK_RST_REG_BITS_VALUE(PLLM_BASE_PLLM_DIVM, divm),
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CLK_RST_REG_BITS_VALUE(PLLM_BASE_PLLM_DIVN, divn),
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CLK_RST_REG_BITS_VALUE(PLLM_BASE_PLLM_DIVP, divp));
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reg::Read(CLKRST + CLK_RST_CONTROLLER_PLLM_BASE);
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/* Set LKCDET. */
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reg::ReadWrite(CLKRST + CLK_RST_CONTROLLER_PLLM_MISC2, CLK_RST_REG_BITS_ENUM(PLLM_MISC2_PLLM_EN_LCKDET, ENABLE));
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/* Set enable. */
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reg::ReadWrite(CLKRST + CLK_RST_CONTROLLER_PLLM_BASE, CLK_RST_REG_BITS_ENUM(PLLM_BASE_PLLM_ENABLE, ENABLE));
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/* Adjust next clock source. */
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if (next_2x == PLLM_UD) {
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reg::SetField(next_clk_src, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, PLLM_UD));
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} else if (next_2x == PLLM_OUT0) {
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reg::SetField(next_clk_src, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, PLLM_OUT0));
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}
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/* Wait for pll to lock. */
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while (!reg::HasValue(CLKRST + CLK_RST_CONTROLLER_PLLM_BASE, CLK_RST_REG_BITS_ENUM(PLLM_BASE_PLLM_LOCK, LOCK))) {
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/* ... */
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}
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}
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return next_clk_src;
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}
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void Dvfs(EmcDvfsTimingTable *dst_timing_tables, EmcDvfsTimingTable *src_timing_tables, bool train) {
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/* Get the old 2x clock source. */
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const u32 prev_2x_clk_src = reg::GetValue(CLKRST + CLK_RST_CONTROLLER_CLK_SOURCE_EMC, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC));
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/* Set g_next_pll. */
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g_next_pll = prev_2x_clk_src == PLLMB_UD || prev_2x_clk_src == PLLMB_OUT0;
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/* Reprogram pll. */
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u32 next_clk_src;
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if (PllReprogram(dst_timing_tables->rate_khz, dst_timing_tables->clk_src_emc, src_timing_tables->rate_khz, src_timing_tables->clk_src_emc)) {
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if (prev_2x_clk_src == PLLMB_UD || prev_2x_clk_src == PLLMB_OUT0) {
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g_next_pll = 0;
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} else if (prev_2x_clk_src == PLLM_UD || prev_2x_clk_src == PLLM_OUT0) {
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g_next_pll = !g_next_pll;
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}
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next_clk_src = ProgramPllm(dst_timing_tables->rate_khz, dst_timing_tables->clk_src_emc, g_next_pll);
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} else {
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next_clk_src = dst_timing_tables->clk_src_emc;
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const u32 next_2x_clk_src = reg::GetField(next_clk_src, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC));
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if (next_2x_clk_src == PLLM_UD || next_2x_clk_src == PLLMB_UD) {
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if (g_next_pll) {
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reg::SetField(next_clk_src, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, PLLMB_UD));
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}
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} else if (next_2x_clk_src == PLLM_OUT0 || next_2x_clk_src == PLLMB_OUT0) {
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if (g_next_pll) {
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reg::SetField(next_clk_src, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, PLLMB_OUT0));
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}
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}
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}
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if (train) {
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TrainFreq(src_timing_tables, dst_timing_tables, next_clk_src);
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if (PllReprogram(dst_timing_tables->rate_khz, dst_timing_tables->clk_src_emc, src_timing_tables->rate_khz, src_timing_tables->clk_src_emc)) {
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g_next_pll = !g_next_pll;
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}
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} else {
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FreqChange(src_timing_tables, dst_timing_tables, next_clk_src);
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}
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}
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}
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void DoMemoryTrainingErista() {
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@ -54,7 +223,20 @@ namespace ams::nxboot {
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ShowFatalError("EmcDvfsTimingTables seem corrupted %" PRIu32 " %" PRIu32 "?\n", src_timing_tables->rate_khz, dst_timing_tables->rate_khz);
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}
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/* TODO */
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/* Check that we should do training. */
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if (src_timing_tables->clk_src_emc != reg::Read(CLKRST + CLK_RST_CONTROLLER_CLK_SOURCE_EMC)) {
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/* Our clock source isn't what's expected, so presumably training has already been done? */
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/* Either way, the safe bet is to skip it. */
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return;
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}
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/* Train 1600MHz. */
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Dvfs(dst_timing_tables, src_timing_tables, true);
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/* Switch to 1600MHz. */
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Dvfs(dst_timing_tables, src_timing_tables, false);
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/* TODO: Periodic compensation */
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}
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}
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@ -23,6 +23,17 @@ namespace ams::nxboot {
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#define EMC0_BASE (0x7001E000)
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#define EMC1_BASE (0x7001F000)
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enum {
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PLLM_OUT0 = CLK_RST_CONTROLLER_CLK_SOURCE_EMC_EMC_2X_CLK_SRC_PLLM_OUT0,
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PLLC_OUT0 = CLK_RST_CONTROLLER_CLK_SOURCE_EMC_EMC_2X_CLK_SRC_PLLC_OUT0,
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PLLP_OUT0 = CLK_RST_CONTROLLER_CLK_SOURCE_EMC_EMC_2X_CLK_SRC_PLLP_OUT0,
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CLK_M = CLK_RST_CONTROLLER_CLK_SOURCE_EMC_EMC_2X_CLK_SRC_CLK_M,
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PLLM_UD = CLK_RST_CONTROLLER_CLK_SOURCE_EMC_EMC_2X_CLK_SRC_PLLM_UD,
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PLLMB_UD = CLK_RST_CONTROLLER_CLK_SOURCE_EMC_EMC_2X_CLK_SRC_PLLMB_UD,
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PLLMB_OUT0 = CLK_RST_CONTROLLER_CLK_SOURCE_EMC_EMC_2X_CLK_SRC_PLLMB_OUT0,
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PLLP_UD = CLK_RST_CONTROLLER_CLK_SOURCE_EMC_EMC_2X_CLK_SRC_PLLP_UD
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};
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#define FOREACH_PER_CHANNEL_BURST_REG(HANDLER) \
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HANDLER(EMC0, EMC_MRW10, emc0_mrw10) \
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HANDLER(EMC1, EMC_MRW10, emc1_mrw10) \
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@ -56,6 +56,12 @@ namespace ams::reg {
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return (EncodeMask(masks) | ...);
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}
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template<typename IntType> requires UnsignedNonConstIntegral<IntType>
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constexpr ALWAYS_INLINE IntType GetField(const IntType &value, const BitsMask mask) { return (value & EncodeMask(mask)) >> GetOffset(mask); }
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template<typename IntType> requires UnsignedNonConstIntegral<IntType>
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constexpr ALWAYS_INLINE void SetField(IntType &value, const BitsValue v) { value = (value & ~EncodeMask(v)) | EncodeValue(v); }
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template<typename IntType> requires UnsignedNonConstIntegral<IntType>
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ALWAYS_INLINE void Write(volatile IntType *reg, std::type_identity_t<IntType> val) { *reg = val; }
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@ -118,6 +118,8 @@ DEFINE_CLK_RST_REG_BIT_ENUM(PLLM_BASE_PLLM_REF_DIS, 29, REF_ENABLE, REF_DISABLE)
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLM_BASE_PLLM_ENABLE, 30, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLM_BASE_PLLM_BYPASSPLL, 31, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLM_MISC2_PLLM_EN_LCKDET, 4, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLD_BASE_CSI_CLK_SRC, 23, BRICK, PLL_D);
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLD_BASE_PLLD_REF_DIS, 29, REF_ENABLE, REF_DISABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLD_BASE_PLLD_ENABLE, 30, DISABLE, ENABLE);
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@ -149,6 +151,10 @@ DEFINE_CLK_RST_REG_BIT_ENUM(PLLC4_BASE_PLLC4_IDDQ, 18, OFF, ON);
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLC4_BASE_PLLC4_LOCK, 27, NOT_LOCK, LOCK_FEQ_AND_PHASE);
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLC4_BASE_PLLC4_ENABLE, 30, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG(PLLMB_BASE_PLLMB_DIVM, 0, 8);
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DEFINE_CLK_RST_REG(PLLMB_BASE_PLLMB_DIVN, 8, 8);
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DEFINE_CLK_RST_REG(PLLMB_BASE_PLLMB_DIVP, 20, 5);
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLMB_BASE_PLLMB_LOCK, 27, NOT_LOCK, LOCK);
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLMB_BASE_PLLMB_ENABLE, 30, DISABLE, ENABLE);
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/* RST_DEVICES */
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DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_HOST1X_HOST1X_CLK_SRC, 29, PLLC4_OUT1, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT2, PLLP_OUT0, CLK_M, PLLA_OUT0, PLLC4_OUT0);
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DEFINE_CLK_RST_REG(CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR, 0, 8);
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DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, 29, PLLM_OUT0, PLLC_OUT0, PLLP_OUT0, CLK_M, PLLM_UD, PLLMB_UD, PLLMB_OUT0, PLLP_UD);
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DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_NVENC_NVENC_CLK_SRC, 29, RESERVED0, PLLC2_OUT0, PLLC_OUT0, PLLC3_OUT0, PLLP_OUT0, RESERVED5, PLLA1_OUT0, CLK_M);
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