mirrors/Atmosphere
1
0
Fork 0
mirror of https://github.com/Atmosphere-NX/Atmosphere.git synced 2024-12-23 02:42:09 +00:00
Code Issues Releases Activity

exo2: Implement SmcReadWriteRegister

Browse source
This commit is contained in:
Michael Scire 2020-05-14 15:57:22 -07:00 committed by SciresM
parent 8c4c1db506
commit e3eadcd2e3
35 changed files with 918 additions and 139 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

30
exosphere2/program/source/smc/secmon_define_access_table.inc Normal file
View file

@ -0,0 +1,30 @@
/*
* Copyright (c) 2018-2020 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
using __ACCESS_TABLE_NAME__ = AccessTable<__ACCESS_TABLE_ADDRESS__, [] {
/* Declare a table. */
std::array<u8, 0x80> table = {};
/* Declare a helper. */
auto SetRegisterAllowed = [&](uintptr_t reg) { SetRegisterTableAllowed(table, reg); };
/* Populate the table. */
#include __ACCESS_TABLE_INC__
return table;
}()>;
static_assert(__ACCESS_TABLE_NAME__::Address >= __ACCESS_TABLE_ADDRESS__);

25
exosphere2/program/source/smc/secmon_define_mc01_access_table.inc Normal file
View file

@ -0,0 +1,25 @@
/*
* Copyright (c) 2018-2020 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#define __ACCESS_TABLE_NAME__ Mc01AccessTable
#define __ACCESS_TABLE_ADDRESS__ 0
#define __ACCESS_TABLE_INC__ "secmon_mc01_access_table_data.inc"
#include "secmon_define_access_table.inc"
#undef __ACCESS_TABLE_INC__
#undef __ACCESS_TABLE_ADDRESS__
#undef __ACCESS_TABLE_NAME__

25
exosphere2/program/source/smc/secmon_define_mc_access_table.inc Normal file
View file

@ -0,0 +1,25 @@
/*
* Copyright (c) 2018-2020 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#define __ACCESS_TABLE_NAME__ McAccessTable
#define __ACCESS_TABLE_ADDRESS__ MemoryRegionPhysicalDeviceMemoryController.GetAddress()
#define __ACCESS_TABLE_INC__ "secmon_mc_access_table_data.inc"
#include "secmon_define_access_table.inc"
#undef __ACCESS_TABLE_INC__
#undef __ACCESS_TABLE_ADDRESS__
#undef __ACCESS_TABLE_NAME__

25
exosphere2/program/source/smc/secmon_define_pmc_access_table.inc Normal file
View file

@ -0,0 +1,25 @@
/*
* Copyright (c) 2018-2020 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#define __ACCESS_TABLE_NAME__ PmcAccessTable
#define __ACCESS_TABLE_ADDRESS__ MemoryRegionPhysicalDevicePmc.GetAddress()
#define __ACCESS_TABLE_INC__ "secmon_pmc_access_table_data.inc"
#include "secmon_define_access_table.inc"
#undef __ACCESS_TABLE_INC__
#undef __ACCESS_TABLE_ADDRESS__
#undef __ACCESS_TABLE_NAME__

43
exosphere2/program/source/smc/secmon_mc01_access_table_data.inc Normal file
View file

@ -0,0 +1,43 @@
/*
* Copyright (c) 2018-2020 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
SetRegisterAllowed(MC_STAT_CONTROL); /* 0x100 */
SetRegisterAllowed(MC_STAT_EMC_CLOCK_LIMIT); /* 0x108 */
SetRegisterAllowed(MC_STAT_EMC_CLOCK_LIMIT_MSBS); /* 0x10C */
SetRegisterAllowed(MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_LO); /* 0x118 */
SetRegisterAllowed(MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_HI); /* 0x11C */
SetRegisterAllowed(MC_STAT_EMC_FILTER_SET0_SPARE); /* 0x124 */
SetRegisterAllowed(MC_STAT_EMC_FILTER_SET0_CLIENT_0); /* 0x128 */
SetRegisterAllowed(MC_STAT_EMC_FILTER_SET0_CLIENT_1); /* 0x12C */
SetRegisterAllowed(MC_STAT_EMC_FILTER_SET0_CLIENT_2); /* 0x130 */
SetRegisterAllowed(MC_STAT_EMC_FILTER_SET0_CLIENT_3); /* 0x134 */
SetRegisterAllowed(MC_STAT_EMC_SET0_COUNT); /* 0x138 */
SetRegisterAllowed(MC_STAT_EMC_SET0_COUNT_MSBS); /* 0x13C */
SetRegisterAllowed(MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_LO); /* 0x158 */
SetRegisterAllowed(MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_HI); /* 0x15C */
SetRegisterAllowed(MC_STAT_EMC_FILTER_SET1_SPARE); /* 0x164 */
SetRegisterAllowed(MC_STAT_EMC_FILTER_SET1_CLIENT_0); /* 0x168 */
SetRegisterAllowed(MC_STAT_EMC_FILTER_SET1_CLIENT_1); /* 0x16C */
SetRegisterAllowed(MC_STAT_EMC_FILTER_SET1_CLIENT_2); /* 0x170 */
SetRegisterAllowed(MC_STAT_EMC_FILTER_SET1_CLIENT_3); /* 0x174 */
SetRegisterAllowed(MC_STAT_EMC_SET1_COUNT); /* 0x178 */
SetRegisterAllowed(MC_STAT_EMC_SET1_COUNT_MSBS); /* 0x17C */
SetRegisterAllowed(MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_UPPER); /* 0xA20 */
SetRegisterAllowed(MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_UPPER); /* 0xA24 */
SetRegisterAllowed(MC_STAT_EMC_FILTER_SET0_CLIENT_4); /* 0xB88 */
SetRegisterAllowed(MC_STAT_EMC_FILTER_SET1_CLIENT_4); /* 0xB8C */
SetRegisterAllowed(MC_STAT_EMC_FILTER_SET0_CLIENT_5); /* 0xBC4 */
SetRegisterAllowed(MC_STAT_EMC_FILTER_SET1_CLIENT_5); /* 0xBC8 */

195
exosphere2/program/source/smc/secmon_mc_access_table_data.inc Normal file
View file

@ -0,0 +1,195 @@
/*
* Copyright (c) 2018-2020 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
SetRegisterAllowed(MC_INTSTATUS); /* 0x000 */
SetRegisterAllowed(MC_INTMASK); /* 0x004 */
SetRegisterAllowed(MC_ERR_STATUS); /* 0x008 */
SetRegisterAllowed(MC_ERR_ADR); /* 0x00C */
SetRegisterAllowed(MC_SMMU_CONFIG); /* 0x010 */
SetRegisterAllowed(MC_SMMU_PTB_ASID); /* 0x01C */
SetRegisterAllowed(MC_SMMU_PTB_DATA); /* 0x020 */
SetRegisterAllowed(MC_SMMU_TLB_FLUSH); /* 0x030 */
SetRegisterAllowed(MC_SMMU_PTC_FLUSH); /* 0x034 */
SetRegisterAllowed(MC_EMEM_CFG); /* 0x050 */
SetRegisterAllowed(MC_EMEM_ADR_CFG); /* 0x054 */
SetRegisterAllowed(MC_EMEM_ARB_CFG); /* 0x090 */
SetRegisterAllowed(MC_EMEM_ARB_OUTSTANDING_REQ); /* 0x094 */
SetRegisterAllowed(MC_EMEM_ARB_TIMING_RCD); /* 0x098 */
SetRegisterAllowed(MC_EMEM_ARB_TIMING_RP); /* 0x09C */
SetRegisterAllowed(MC_EMEM_ARB_TIMING_RC); /* 0x0A0 */
SetRegisterAllowed(MC_EMEM_ARB_TIMING_RAS); /* 0x0A4 */
SetRegisterAllowed(MC_EMEM_ARB_TIMING_FAW); /* 0x0A8 */
SetRegisterAllowed(MC_EMEM_ARB_TIMING_RRD); /* 0x0AC */
SetRegisterAllowed(MC_EMEM_ARB_TIMING_RAP2PRE); /* 0x0B0 */
SetRegisterAllowed(MC_EMEM_ARB_TIMING_WAP2PRE); /* 0x0B4 */
SetRegisterAllowed(MC_EMEM_ARB_TIMING_R2R); /* 0x0B8 */
SetRegisterAllowed(MC_EMEM_ARB_TIMING_W2W); /* 0x0BC */
SetRegisterAllowed(MC_EMEM_ARB_TIMING_R2W); /* 0x0C0 */
SetRegisterAllowed(MC_EMEM_ARB_TIMING_W2R); /* 0x0C4 */
SetRegisterAllowed(MC_EMEM_ARB_MISC2); /* 0x0C8 */
SetRegisterAllowed(MC_EMEM_ARB_DA_TURNS); /* 0x0D0 */
SetRegisterAllowed(MC_EMEM_ARB_DA_COVERS); /* 0x0D4 */
SetRegisterAllowed(MC_EMEM_ARB_MISC0); /* 0x0D8 */
SetRegisterAllowed(MC_EMEM_ARB_MISC1); /* 0x0DC */
SetRegisterAllowed(MC_EMEM_ARB_RING1_THROTTLE); /* 0x0E0 */
SetRegisterAllowed(MC_CLIENT_HOTRESET_CTRL); /* 0x200 */
SetRegisterAllowed(MC_CLIENT_HOTRESET_STATUS); /* 0x204 */
SetRegisterAllowed(MC_SMMU_AFI_ASID); /* 0x238 */
SetRegisterAllowed(MC_SMMU_DC_ASID); /* 0x240 */
SetRegisterAllowed(MC_SMMU_DCB_ASID); /* 0x244 */
SetRegisterAllowed(MC_SMMU_HC_ASID); /* 0x250 */
SetRegisterAllowed(MC_SMMU_HDA_ASID); /* 0x254 */
SetRegisterAllowed(MC_SMMU_ISP2_ASID); /* 0x258 */
SetRegisterAllowed(MC_SMMU_NVENC_ASID); /* 0x264 */
SetRegisterAllowed(MC_SMMU_NV_ASID); /* 0x268 */
SetRegisterAllowed(MC_SMMU_NV2_ASID); /* 0x26C */
SetRegisterAllowed(MC_SMMU_PPCS_ASID); /* 0x270 */
SetRegisterAllowed(MC_SMMU_SATA_ASID); /* 0x274 */
SetRegisterAllowed(MC_SMMU_VI_ASID); /* 0x280 */
SetRegisterAllowed(MC_SMMU_VIC_ASID); /* 0x284 */
SetRegisterAllowed(MC_SMMU_XUSB_HOST_ASID); /* 0x288 */
SetRegisterAllowed(MC_SMMU_XUSB_DEV_ASID); /* 0x28C */
SetRegisterAllowed(MC_SMMU_TSEC_ASID); /* 0x294 */
SetRegisterAllowed(MC_LATENCY_ALLOWANCE_AVPC_0); /* 0x2E4 */
SetRegisterAllowed(MC_LATENCY_ALLOWANCE_DC_0); /* 0x2E8 */
SetRegisterAllowed(MC_LATENCY_ALLOWANCE_DC_1); /* 0x2EC */
SetRegisterAllowed(MC_LATENCY_ALLOWANCE_DCB_0); /* 0x2F4 */
SetRegisterAllowed(MC_LATENCY_ALLOWANCE_DCB_1); /* 0x2F8 */
SetRegisterAllowed(MC_LATENCY_ALLOWANCE_HC_0); /* 0x310 */
SetRegisterAllowed(MC_LATENCY_ALLOWANCE_HC_1); /* 0x314 */
SetRegisterAllowed(MC_LATENCY_ALLOWANCE_MPCORE_0); /* 0x320 */
SetRegisterAllowed(MC_LATENCY_ALLOWANCE_NVENC_0); /* 0x328 */
SetRegisterAllowed(MC_LATENCY_ALLOWANCE_PPCS_0); /* 0x344 */
SetRegisterAllowed(MC_LATENCY_ALLOWANCE_PPCS_1); /* 0x348 */
SetRegisterAllowed(MC_LATENCY_ALLOWANCE_ISP2_0); /* 0x370 */
SetRegisterAllowed(MC_LATENCY_ALLOWANCE_ISP2_1); /* 0x374 */
SetRegisterAllowed(MC_LATENCY_ALLOWANCE_XUSB_0); /* 0x37C */
SetRegisterAllowed(MC_LATENCY_ALLOWANCE_XUSB_1); /* 0x380 */
SetRegisterAllowed(MC_LATENCY_ALLOWANCE_TSEC_0); /* 0x390 */
SetRegisterAllowed(MC_LATENCY_ALLOWANCE_VIC_0); /* 0x394 */
SetRegisterAllowed(MC_LATENCY_ALLOWANCE_VI2_0); /* 0x398 */
SetRegisterAllowed(MC_LATENCY_ALLOWANCE_GPU_0); /* 0x3AC */
SetRegisterAllowed(MC_LATENCY_ALLOWANCE_SDMMCA_0); /* 0x3B8 */
SetRegisterAllowed(MC_LATENCY_ALLOWANCE_SDMMCAA_0); /* 0x3BC */
SetRegisterAllowed(MC_LATENCY_ALLOWANCE_SDMMC_0); /* 0x3C0 */
SetRegisterAllowed(MC_LATENCY_ALLOWANCE_SDMMCAB_0); /* 0x3C4 */
SetRegisterAllowed(MC_LATENCY_ALLOWANCE_NVDEC_0); /* 0x3D8 */
SetRegisterAllowed(MC_LATENCY_ALLOWANCE_GPU2_0); /* 0x3E8 */
SetRegisterAllowed(MC_DIS_PTSA_RATE); /* 0x41C */
SetRegisterAllowed(MC_DIS_PTSA_MIN); /* 0x420 */
SetRegisterAllowed(MC_DIS_PTSA_MAX); /* 0x424 */
SetRegisterAllowed(MC_DISB_PTSA_RATE); /* 0x428 */
SetRegisterAllowed(MC_DISB_PTSA_MIN); /* 0x42C */
SetRegisterAllowed(MC_DISB_PTSA_MAX); /* 0x430 */
SetRegisterAllowed(MC_VE_PTSA_RATE); /* 0x434 */
SetRegisterAllowed(MC_VE_PTSA_MIN); /* 0x438 */
SetRegisterAllowed(MC_VE_PTSA_MAX); /* 0x43C */
SetRegisterAllowed(MC_MLL_MPCORER_PTSA_RATE); /* 0x44C */
SetRegisterAllowed(MC_RING1_PTSA_RATE); /* 0x47C */
SetRegisterAllowed(MC_RING1_PTSA_MIN); /* 0x480 */
SetRegisterAllowed(MC_RING1_PTSA_MAX); /* 0x484 */
SetRegisterAllowed(MC_PCX_PTSA_RATE); /* 0x4AC */
SetRegisterAllowed(MC_PCX_PTSA_MIN); /* 0x4B0 */
SetRegisterAllowed(MC_PCX_PTSA_MAX); /* 0x4B4 */
SetRegisterAllowed(MC_MSE_PTSA_RATE); /* 0x4C4 */
SetRegisterAllowed(MC_MSE_PTSA_MIN); /* 0x4C8 */
SetRegisterAllowed(MC_MSE_PTSA_MAX); /* 0x4CC */
SetRegisterAllowed(MC_AHB_PTSA_RATE); /* 0x4DC */
SetRegisterAllowed(MC_AHB_PTSA_MIN); /* 0x4E0 */
SetRegisterAllowed(MC_AHB_PTSA_MAX); /* 0x4E4 */
SetRegisterAllowed(MC_APB_PTSA_RATE); /* 0x4E8 */
SetRegisterAllowed(MC_APB_PTSA_MIN); /* 0x4EC */
SetRegisterAllowed(MC_APB_PTSA_MAX); /* 0x4F0 */
SetRegisterAllowed(MC_FTOP_PTSA_RATE); /* 0x50C */
SetRegisterAllowed(MC_HOST_PTSA_RATE); /* 0x518 */
SetRegisterAllowed(MC_HOST_PTSA_MIN); /* 0x51C */
SetRegisterAllowed(MC_HOST_PTSA_MAX); /* 0x520 */
SetRegisterAllowed(MC_USBX_PTSA_RATE); /* 0x524 */
SetRegisterAllowed(MC_USBX_PTSA_MIN); /* 0x528 */
SetRegisterAllowed(MC_USBX_PTSA_MAX); /* 0x52C */
SetRegisterAllowed(MC_USBD_PTSA_RATE); /* 0x530 */
SetRegisterAllowed(MC_USBD_PTSA_MIN); /* 0x534 */
SetRegisterAllowed(MC_USBD_PTSA_MAX); /* 0x538 */
SetRegisterAllowed(MC_GK_PTSA_RATE); /* 0x53C */
SetRegisterAllowed(MC_GK_PTSA_MIN); /* 0x540 */
SetRegisterAllowed(MC_GK_PTSA_MAX); /* 0x544 */
SetRegisterAllowed(MC_AUD_PTSA_RATE); /* 0x548 */
SetRegisterAllowed(MC_AUD_PTSA_MIN); /* 0x54C */
SetRegisterAllowed(MC_AUD_PTSA_MAX); /* 0x550 */
SetRegisterAllowed(MC_VICPC_PTSA_RATE); /* 0x554 */
SetRegisterAllowed(MC_VICPC_PTSA_MIN); /* 0x558 */
SetRegisterAllowed(MC_VICPC_PTSA_MAX); /* 0x55C */
SetRegisterAllowed(MC_JPG_PTSA_RATE); /* 0x584 */
SetRegisterAllowed(MC_JPG_PTSA_MIN); /* 0x588 */
SetRegisterAllowed(MC_JPG_PTSA_MAX); /* 0x58C */
SetRegisterAllowed(MC_GK2_PTSA_RATE); /* 0x610 */
SetRegisterAllowed(MC_GK2_PTSA_MIN); /* 0x614 */
SetRegisterAllowed(MC_GK2_PTSA_MAX); /* 0x618 */
SetRegisterAllowed(MC_SDM_PTSA_RATE); /* 0x61C */
SetRegisterAllowed(MC_SDM_PTSA_MIN); /* 0x620 */
SetRegisterAllowed(MC_SDM_PTSA_MAX); /* 0x624 */
SetRegisterAllowed(MC_HDAPC_PTSA_RATE); /* 0x628 */
SetRegisterAllowed(MC_HDAPC_PTSA_MIN); /* 0x62C */
SetRegisterAllowed(MC_HDAPC_PTSA_MAX); /* 0x630 */
SetRegisterAllowed(MC_SEC_CARVEOUT_BOM); /* 0x670 */
SetRegisterAllowed(MC_SEC_CARVEOUT_SIZE_MB); /* 0x674 */
SetRegisterAllowed(MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A); /* 0x690 */
SetRegisterAllowed(MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB); /* 0x694 */
SetRegisterAllowed(MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B); /* 0x698 */
SetRegisterAllowed(MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB); /* 0x69C */
SetRegisterAllowed(MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C); /* 0x6A0 */
SetRegisterAllowed(MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB); /* 0x6A4 */
SetRegisterAllowed(MC_EMEM_ARB_TIMING_RFCPB); /* 0x6C0 */
SetRegisterAllowed(MC_EMEM_ARB_TIMING_CCDMW); /* 0x6C4 */
SetRegisterAllowed(MC_EMEM_ARB_REFPB_HP_CTRL); /* 0x6F0 */
SetRegisterAllowed(MC_EMEM_ARB_REFPB_BANK_CTRL); /* 0x6F4 */
SetRegisterAllowed(MC_PTSA_GRANT_DECREMENT); /* 0x960 */
SetRegisterAllowed(MC_CLIENT_HOTRESET_CTRL_1); /* 0x970 */
SetRegisterAllowed(MC_CLIENT_HOTRESET_STATUS_1); /* 0x974 */
SetRegisterAllowed(MC_SMMU_PTC_FLUSH_1); /* 0x9B8 */
SetRegisterAllowed(MC_SMMU_DC1_ASID); /* 0xA88 */
SetRegisterAllowed(MC_SMMU_SDMMC1A_ASID); /* 0xA94 */
SetRegisterAllowed(MC_SMMU_SDMMC2A_ASID); /* 0xA98 */
SetRegisterAllowed(MC_SMMU_SDMMC3A_ASID); /* 0xA9C */
SetRegisterAllowed(MC_SMMU_SDMMC4A_ASID); /* 0xAA0 */
SetRegisterAllowed(MC_SMMU_ISP2B_ASID); /* 0xAA4 */
SetRegisterAllowed(MC_SMMU_GPU_ASID); /* 0xAA8 */
SetRegisterAllowed(MC_SMMU_GPUB_ASID); /* 0xAAC */
SetRegisterAllowed(MC_SMMU_PPCS2_ASID); /* 0xAB0 */
SetRegisterAllowed(MC_SMMU_NVDEC_ASID); /* 0xAB4 */
SetRegisterAllowed(MC_SMMU_APE_ASID); /* 0xAB8 */
SetRegisterAllowed(MC_SMMU_SE_ASID); /* 0xABC */
SetRegisterAllowed(MC_SMMU_NVJPG_ASID); /* 0xAC0 */
SetRegisterAllowed(MC_SMMU_HC1_ASID); /* 0xAC4 */
SetRegisterAllowed(MC_SMMU_SE1_ASID); /* 0xAC8 */
SetRegisterAllowed(MC_SMMU_AXIAP_ASID); /* 0xACC */
SetRegisterAllowed(MC_SMMU_ETR_ASID); /* 0xAD0 */
SetRegisterAllowed(MC_SMMU_TSECB_ASID); /* 0xAD4 */
SetRegisterAllowed(MC_SMMU_TSEC1_ASID); /* 0xAD8 */
SetRegisterAllowed(MC_SMMU_TSECB1_ASID); /* 0xADC */
SetRegisterAllowed(MC_SMMU_NVDEC1_ASID); /* 0xAE0 */
SetRegisterAllowed(MC_EMEM_ARB_DHYST_CTRL); /* 0xBCC */
SetRegisterAllowed(MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0); /* 0xBD0 */
SetRegisterAllowed(MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1); /* 0xBD4 */
SetRegisterAllowed(MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2); /* 0xBD8 */
SetRegisterAllowed(MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3); /* 0xBDC */
SetRegisterAllowed(MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4); /* 0xBE0 */
SetRegisterAllowed(MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5); /* 0xBE4 */
SetRegisterAllowed(MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6); /* 0xBE8 */
SetRegisterAllowed(MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7); /* 0xBEC */
SetRegisterAllowed(MC_ERR_GENERALIZED_CARVEOUT_STATUS); /* 0xC00 */
SetRegisterAllowed(MC_SECURITY_CARVEOUT2_BOM); /* 0xC5C */
SetRegisterAllowed(MC_SECURITY_CARVEOUT3_BOM); /* 0xCAC */

47
exosphere2/program/source/smc/secmon_pmc_access_table_data.inc Normal file
View file

@ -0,0 +1,47 @@
/*
* Copyright (c) 2018-2020 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
SetRegisterAllowed(APBDEV_PMC_CNTRL); /* 0x000 */
SetRegisterAllowed(APBDEV_PMC_WAKE_MASK); /* 0x00C */
SetRegisterAllowed(APBDEV_PMC_WAKE_LVL); /* 0x010 */
SetRegisterAllowed(APBDEV_PMC_WAKE_STATUS); /* 0x014 */
SetRegisterAllowed(APBDEV_PMC_DPD_PADS_ORIDE); /* 0x01C */
SetRegisterAllowed(APBDEV_PMC_DPD_SAMPLE); /* 0x020 */
SetRegisterAllowed(APBDEV_PMC_CLAMP_STATUS); /* 0x02C */
SetRegisterAllowed(APBDEV_PMC_PWRGATE_TOGGLE); /* 0x030 */
SetRegisterAllowed(APBDEV_PMC_REMOVE_CLAMPING_CMD ); /* 0x034 */
SetRegisterAllowed(APBDEV_PMC_PWRGATE_STATUS); /* 0x038 */
SetRegisterAllowed(APBDEV_PMC_PWRGOOD_TIMER); /* 0x03C */
SetRegisterAllowed(APBDEV_PMC_BLINK_TIMER); /* 0x040 */
SetRegisterAllowed(APBDEV_PMC_NO_IOPOWER); /* 0x044 */
SetRegisterAllowed(APBDEV_PMC_PWR_DET); /* 0x048 */
SetRegisterAllowed(APBDEV_PMC_AUTO_WAKE_LVL_MASK); /* 0x0DC */
SetRegisterAllowed(APBDEV_PMC_WAKE_DELAY); /* 0x0E0 */
SetRegisterAllowed(APBDEV_PMC_PWR_DET_VAL); /* 0x0E4 */
SetRegisterAllowed(APBDEV_PMC_WAKE2_MASK); /* 0x160 */
SetRegisterAllowed(APBDEV_PMC_WAKE2_LVL); /* 0x164 */
SetRegisterAllowed(APBDEV_PMC_WAKE2_STATUS); /* 0x168 */
SetRegisterAllowed(APBDEV_PMC_AUTO_WAKE2_LVL_MASK ); /* 0x170 */
SetRegisterAllowed(APBDEV_PMC_CLK_OUT_CNTRL); /* 0x1A8 */
SetRegisterAllowed(APBDEV_PMC_IO_DPD_REQ); /* 0x1B8 */
SetRegisterAllowed(APBDEV_PMC_IO_DPD_STATUS); /* 0x1BC */
SetRegisterAllowed(APBDEV_PMC_IO_DPD2_REQ); /* 0x1C0 */
SetRegisterAllowed(APBDEV_PMC_IO_DPD2_STATUS); /* 0x1C4 */
SetRegisterAllowed(APBDEV_PMC_SEL_DPD_TIM); /* 0x1C8 */
SetRegisterAllowed(APBDEV_PMC_TSC_MULT); /* 0x2B4 */
SetRegisterAllowed(APBDEV_PMC_GPU_RG_CNTRL); /* 0x2D4 */
SetRegisterAllowed(APBDEV_PMC_CNTRL2); /* 0x440 */
SetRegisterAllowed(APBDEV_PMC_WAKE_DEBOUNCE_EN); /* 0x4D8 */

12
exosphere2/program/source/smc/secmon_smc_aes.cpp
View file

@ -19,32 +19,32 @@
namespace ams::secmon::smc {
SmcResult SmcGenerateAesKek(const SmcArguments &args) {
SmcResult SmcGenerateAesKek(SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
}
SmcResult SmcLoadAesKey(const SmcArguments &args) {
SmcResult SmcLoadAesKey(SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
}
SmcResult SmcComputeAes(const SmcArguments &args) {
SmcResult SmcComputeAes(SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
}
SmcResult SmcGenerateSpecificAesKey(const SmcArguments &args) {
SmcResult SmcGenerateSpecificAesKey(SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
}
SmcResult SmcComputeCmac(const SmcArguments &args) {
SmcResult SmcComputeCmac(SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
}
SmcResult SmcLoadPreparedAesKey(const SmcArguments &args) {
SmcResult SmcLoadPreparedAesKey(SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
}

12
exosphere2/program/source/smc/secmon_smc_aes.hpp
View file

@ -19,11 +19,11 @@
namespace ams::secmon::smc {
SmcResult SmcGenerateAesKek(const SmcArguments &args);
SmcResult SmcLoadAesKey(const SmcArguments &args);
SmcResult SmcComputeAes(const SmcArguments &args);
SmcResult SmcGenerateSpecificAesKey(const SmcArguments &args);
SmcResult SmcComputeCmac(const SmcArguments &args);
SmcResult SmcLoadPreparedAesKey(const SmcArguments &args);
SmcResult SmcGenerateAesKek(SmcArguments &args);
SmcResult SmcLoadAesKey(SmcArguments &args);
SmcResult SmcComputeAes(SmcArguments &args);
SmcResult SmcGenerateSpecificAesKey(SmcArguments &args);
SmcResult SmcComputeCmac(SmcArguments &args);
SmcResult SmcLoadPreparedAesKey(SmcArguments &args);
}

2
exosphere2/program/source/smc/secmon_smc_carveout.cpp
View file

@ -19,7 +19,7 @@
namespace ams::secmon::smc {
SmcResult SmcSetKernelCarveoutRegion(const SmcArguments &args) {
SmcResult SmcSetKernelCarveoutRegion(SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
}

2
exosphere2/program/source/smc/secmon_smc_carveout.hpp
View file

@ -19,6 +19,6 @@
namespace ams::secmon::smc {
SmcResult SmcSetKernelCarveoutRegion(const SmcArguments &args);
SmcResult SmcSetKernelCarveoutRegion(SmcArguments &args);
}

8
exosphere2/program/source/smc/secmon_smc_device_unique_data.cpp
View file

@ -19,23 +19,23 @@
namespace ams::secmon::smc {
SmcResult SmcDecryptDeviceUniqueData(const SmcArguments &args) {
SmcResult SmcDecryptDeviceUniqueData(SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
}
SmcResult SmcReencryptDeviceUniqueData(const SmcArguments &args) {
SmcResult SmcReencryptDeviceUniqueData(SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
}
/* Legacy APIs. */
SmcResult SmcDecryptAndImportEsDeviceKey(const SmcArguments &args) {
SmcResult SmcDecryptAndImportEsDeviceKey(SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
}
SmcResult SmcDecryptAndImportLotusKey(const SmcArguments &args) {
SmcResult SmcDecryptAndImportLotusKey(SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
}

8
exosphere2/program/source/smc/secmon_smc_device_unique_data.hpp
View file

@ -19,11 +19,11 @@
namespace ams::secmon::smc {
SmcResult SmcDecryptDeviceUniqueData(const SmcArguments &args);
SmcResult SmcReencryptDeviceUniqueData(const SmcArguments &args);
SmcResult SmcDecryptDeviceUniqueData(SmcArguments &args);
SmcResult SmcReencryptDeviceUniqueData(SmcArguments &args);
/* Legacy APIs. */
SmcResult SmcDecryptAndImportEsDeviceKey(const SmcArguments &args);
SmcResult SmcDecryptAndImportLotusKey(const SmcArguments &args);
SmcResult SmcDecryptAndImportEsDeviceKey(SmcArguments &args);
SmcResult SmcDecryptAndImportLotusKey(SmcArguments &args);
}

2
exosphere2/program/source/smc/secmon_smc_error.cpp
View file

@ -19,7 +19,7 @@
namespace ams::secmon::smc {
SmcResult SmcShowError(const SmcArguments &args) {
SmcResult SmcShowError(SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
}

2
exosphere2/program/source/smc/secmon_smc_error.hpp
View file

@ -19,6 +19,6 @@
namespace ams::secmon::smc {
SmcResult SmcShowError(const SmcArguments &args);
SmcResult SmcShowError(SmcArguments &args);
}

4
exosphere2/program/source/smc/secmon_smc_es.cpp
View file

@ -19,12 +19,12 @@
namespace ams::secmon::smc {
SmcResult SmcPrepareEsDeviceUniqueKey(const SmcArguments &args) {
SmcResult SmcPrepareEsDeviceUniqueKey(SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
}
SmcResult SmcPrepareEsCommonKey(const SmcArguments &args) {
SmcResult SmcPrepareEsCommonKey(SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
}

4
exosphere2/program/source/smc/secmon_smc_es.hpp
View file

@ -26,7 +26,7 @@ namespace ams::secmon::smc {
EsKeyType_Count = 2,
};
SmcResult SmcPrepareEsDeviceUniqueKey(const SmcArguments &args);
SmcResult SmcPrepareEsCommonKey(const SmcArguments &args);
SmcResult SmcPrepareEsDeviceUniqueKey(SmcArguments &args);
SmcResult SmcPrepareEsCommonKey(SmcArguments &args);
}

2
exosphere2/program/source/smc/secmon_smc_handler.cpp
View file

@ -207,7 +207,7 @@ namespace ams::secmon::smc {
return (info.restriction_mask & secmon::GetRestrictedSmcMask()) != 0;
}
SmcResult InvokeSmcHandler(const HandlerInfo &info, const SmcArguments &args) {
SmcResult InvokeSmcHandler(const HandlerInfo &info, SmcArguments &args) {
/* Check if the smc is restricted. */
if (AMS_UNLIKELY(IsHandlerRestricted(info))) {
return SmcResult::NotPermitted;

2
exosphere2/program/source/smc/secmon_smc_handler.hpp
View file

@ -19,6 +19,6 @@
namespace ams::secmon::smc {
using SmcHandler = SmcResult (*)(const SmcArguments &args);
using SmcHandler = SmcResult (*)(SmcArguments &args);
}

8
exosphere2/program/source/smc/secmon_smc_info.cpp
View file

@ -19,23 +19,23 @@
namespace ams::secmon::smc {
SmcResult SmcGetConfigUser(const SmcArguments &args) {
SmcResult SmcGetConfigUser(SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
}
SmcResult SmcGetConfigKern(const SmcArguments &args) {
SmcResult SmcGetConfigKern(SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
}
SmcResult SmcSetConfig(const SmcArguments &args) {
SmcResult SmcSetConfig(SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
}
/* This is an atmosphere extension smc. */
SmcResult SmcGetEmummcConfig(const SmcArguments &args) {
SmcResult SmcGetEmummcConfig(SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
}

8
exosphere2/program/source/smc/secmon_smc_info.hpp
View file

@ -49,11 +49,11 @@ namespace ams::secmon::smc {
ExosphereAllowCalWrites = 65006,
};
SmcResult SmcGetConfigUser(const SmcArguments &args);
SmcResult SmcGetConfigKern(const SmcArguments &args);
SmcResult SmcSetConfig(const SmcArguments &args);
SmcResult SmcGetConfigUser(SmcArguments &args);
SmcResult SmcGetConfigKern(SmcArguments &args);
SmcResult SmcSetConfig(SmcArguments &args);
/* This is an atmosphere extension smc. */
SmcResult SmcGetEmummcConfig(const SmcArguments &args);
SmcResult SmcGetEmummcConfig(SmcArguments &args);
}

4
exosphere2/program/source/smc/secmon_smc_memory_access.cpp
View file

@ -20,12 +20,12 @@
namespace ams::secmon::smc {
/* This is an atmosphere extension smc. */
SmcResult SmcIramCopy(const SmcArguments &args) {
SmcResult SmcIramCopy(SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
}
SmcResult SmcWriteAddress(const SmcArguments &args) {
SmcResult SmcWriteAddress(SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
}

4
exosphere2/program/source/smc/secmon_smc_memory_access.hpp
View file

@ -20,7 +20,7 @@
namespace ams::secmon::smc {
/* This is an atmosphere extension smc. */
SmcResult SmcIramCopy(const SmcArguments &args);
SmcResult SmcWriteAddress(const SmcArguments &args);
SmcResult SmcIramCopy(SmcArguments &args);
SmcResult SmcWriteAddress(SmcArguments &args);
}

6
exosphere2/program/source/smc/secmon_smc_power_management.cpp
View file

@ -96,12 +96,12 @@ namespace ams::secmon::smc {
}
SmcResult SmcPowerOffCpu(const SmcArguments &args) {
SmcResult SmcPowerOffCpu(SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
}
SmcResult SmcPowerOnCpu(const SmcArguments &args) {
SmcResult SmcPowerOnCpu(SmcArguments &args) {
/* Get and validate the core to power on. */
const int which_core = args.r[1];
if (!(0 <= which_core && which_core < NumCores)) {
@ -128,7 +128,7 @@ namespace ams::secmon::smc {
return SmcResult::PsciSuccess;
}
SmcResult SmcSuspendCpu(const SmcArguments &args) {
SmcResult SmcSuspendCpu(SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
}

6
exosphere2/program/source/smc/secmon_smc_power_management.hpp
View file

@ -19,10 +19,10 @@
namespace ams::secmon::smc {
SmcResult SmcPowerOffCpu(const SmcArguments &args);
SmcResult SmcPowerOnCpu(const SmcArguments &args);
SmcResult SmcPowerOffCpu(SmcArguments &args);
SmcResult SmcPowerOnCpu(SmcArguments &args);
SmcResult SmcSuspendCpu(const SmcArguments &args);
SmcResult SmcSuspendCpu(SmcArguments &args);
bool IsChargerHiZModeEnabled();
void SetChargerHiZModeEnabled(bool en);

4
exosphere2/program/source/smc/secmon_smc_random.cpp
View file

@ -19,12 +19,12 @@
namespace ams::secmon::smc {
SmcResult SmcGenerateRandomBytes(const SmcArguments &args) {
SmcResult SmcGenerateRandomBytes(SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
}
SmcResult SmcGenerateRandomBytesNonBlocking(const SmcArguments &args) {
SmcResult SmcGenerateRandomBytesNonBlocking(SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
}

4
exosphere2/program/source/smc/secmon_smc_random.hpp
View file

@ -19,7 +19,7 @@
namespace ams::secmon::smc {
SmcResult SmcGenerateRandomBytes(const SmcArguments &args);
SmcResult SmcGenerateRandomBytesNonBlocking(const SmcArguments &args);
SmcResult SmcGenerateRandomBytes(SmcArguments &args);
SmcResult SmcGenerateRandomBytesNonBlocking(SmcArguments &args);
}

176
exosphere2/program/source/smc/secmon_smc_register_access.cpp
View file

@ -19,9 +19,179 @@
namespace ams::secmon::smc {
SmcResult SmcReadWriteRegister(const SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
namespace {
template<size_t N>
constexpr void SetRegisterTableAllowed(std::array<u8, N> &arr, uintptr_t reg) {
/* All registers should be four byte aligned. */
if (reg % sizeof(u32) != 0) {
__builtin_unreachable();
}
/* Reduce the register to an index. */
reg /= sizeof(u32);
/* Get the index and mask. */
const auto index = reg / BITSIZEOF(u8);
const auto mask = (1u << (reg % BITSIZEOF(u8)));
/* Check that the permission bit isn't already set. */
if ((arr[index] & mask) != 0) {
__builtin_unreachable();
}
/* Set the permission bit. */
arr[index] |= mask;
/* Ensure that indices are set in sorted order. */
for (auto i = (reg % BITSIZEOF(u8)) + 1; i < 8; ++i) {
if ((arr[index] & (1u << i)) != 0) {
__builtin_unreachable();
}
}
for (auto i = index + 1; i < arr.size(); ++i) {
if (arr[i] != 0) {
__builtin_unreachable();
}
}
}
template<size_t N>
consteval std::pair<size_t, size_t> GetReducedAccessTableInfo(const std::array<u8, N> &arr) {
for (int last = arr.size() - 1; last >= 0; --last) {
if (arr[last] != 0) {
const int end = last + 1;
for (int start = 0; start < end; ++start) {
if (arr[start] != 0) {
return std::make_pair(static_cast<size_t>(start), static_cast<size_t>(end));
}
}
return std::make_pair(static_cast<size_t>(0), static_cast<size_t>(end));
}
}
/* All empty perm table is disallowed. */
__builtin_unreachable();
}
template<u32 _Address, auto RawTable>
struct AccessTable {
static constexpr inline auto ReducedAccessTableInfo = GetReducedAccessTableInfo(RawTable);
static constexpr inline size_t ReducedAccessTableSize = ReducedAccessTableInfo.second - ReducedAccessTableInfo.first;
static constexpr inline auto ReducedAccessTable = []() -> std::array<u8, ReducedAccessTableSize> {
std::array<u8, ReducedAccessTableSize> reduced = {};
for (size_t i = ReducedAccessTableInfo.first; i < ReducedAccessTableInfo.second; ++i) {
reduced[i - ReducedAccessTableInfo.first] = RawTable[i];
}
return reduced;
}();
static constexpr u32 Address = _Address + (ReducedAccessTableInfo.first * sizeof(u32) * BITSIZEOF(u8));
static constexpr u32 Size = static_cast<u32>(ReducedAccessTableSize * sizeof(u32) * BITSIZEOF(u8));
static_assert(Size <= 0x1000);
};
struct AccessTableEntry {
const u8 * const table;
uintptr_t virtual_address;
u32 address;
u32 size;
};
/* Include the access tables. */
#include "secmon_define_pmc_access_table.inc"
#include "secmon_define_mc_access_table.inc"
#include "secmon_define_mc01_access_table.inc"
constexpr const AccessTableEntry AccessTables[] = {
{ PmcAccessTable::ReducedAccessTable.data(), MemoryRegionVirtualDevicePmc.GetAddress(), PmcAccessTable::Address, PmcAccessTable::Size, },
{ McAccessTable::ReducedAccessTable.data(), MemoryRegionVirtualDeviceMemoryController.GetAddress(), McAccessTable::Address, McAccessTable::Size, },
{ Mc01AccessTable::ReducedAccessTable.data(), MemoryRegionVirtualDeviceMemoryController0.GetAddress(), Mc01AccessTable::Address + MemoryRegionPhysicalDeviceMemoryController0.GetAddress(), Mc01AccessTable::Size, },
{ Mc01AccessTable::ReducedAccessTable.data(), MemoryRegionVirtualDeviceMemoryController1.GetAddress(), Mc01AccessTable::Address + MemoryRegionPhysicalDeviceMemoryController1.GetAddress(), Mc01AccessTable::Size, },
};
constexpr bool IsAccessAllowed(const AccessTableEntry &entry, uintptr_t address) {
/* Check if the address is within range. */
if (!(entry.address <= address && address < entry.address + entry.size)) {
return false;
}
/* Get the offset. */
const auto offset = address - entry.address;
/* Convert it to an index. */
const auto reg_index = offset / sizeof(u32);
/* Get the bit fields. */
const auto index = reg_index / BITSIZEOF(u8);
const auto mask = (1u << (reg_index % BITSIZEOF(u8)));
/* Validate that we're not going out of bounds. */
if (index >= entry.size / sizeof(u32)) {
return false;
}
return (entry.table[index] & mask) != 0;
}
constexpr const AccessTableEntry *GetAccessTableEntry(uintptr_t address) {
for (const auto &entry : AccessTables) {
if (IsAccessAllowed(entry, address)) {
return std::addressof(entry);
}
}
return nullptr;
}
}
SmcResult SmcReadWriteRegister(SmcArguments &args) {
/* Get the arguments. */
const uintptr_t address = args.r[1];
const u32 mask = args.r[2];
const u32 value = args.r[3];
/* Validate that the address is aligned. */
if (!util::IsAligned(address, alignof(u32))) {
return SmcResult::InvalidArgument;
}
/* Find the access table. */
const AccessTableEntry * const entry = GetAccessTableEntry(address);
/* If we have no table, don't perform the write. */
if (entry == nullptr) {
/* For no clearly discernable reason, SmcReadWriteRegister returns success despite not doing the read/write */
/* when accessing the SMMU controls for the BPMP and for APB-DMA. */
/* This is "probably" to fuck with hackers who got access to the SMC and are trying to get control of the */
/* BPMP to exploit jamais vu, deja vu, or other related DMA/wake-from-sleep vulnerabilities. */
constexpr uintptr_t MC = MemoryRegionVirtualDeviceMemoryController.GetAddress();
if (address == (MC + MC_SMMU_AVPC_ASID) || address == (MC + MC_SMMU_PPCS1_ASID)) {
return SmcResult::Success;
}
return SmcResult::InvalidArgument;
}
/* Get the address to read or write. */
const uintptr_t virtual_address = entry->virtual_address + (address - entry->address);
u32 out = 0;
if (mask != ~static_cast<u32>(0)) {
out = reg::Read(virtual_address);
}
if (mask != static_cast<u32>(0)) {
reg::Write(virtual_address, (out & ~mask) | (value & mask));
}
args.r[1] = out;
return SmcResult::Success;
}
}

2
exosphere2/program/source/smc/secmon_smc_register_access.hpp
View file

@ -19,6 +19,6 @@
namespace ams::secmon::smc {
SmcResult SmcReadWriteRegister(const SmcArguments &args);
SmcResult SmcReadWriteRegister(SmcArguments &args);
}

4
exosphere2/program/source/smc/secmon_smc_result.cpp
View file

@ -19,12 +19,12 @@
namespace ams::secmon::smc {
SmcResult SmcGetResult(const SmcArguments &args) {
SmcResult SmcGetResult(SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
}
SmcResult SmcGetResultData(const SmcArguments &args) {
SmcResult SmcGetResultData(SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
}

4
exosphere2/program/source/smc/secmon_smc_result.hpp
View file

@ -25,7 +25,7 @@ namespace ams::secmon::smc {
void CancelAsyncOperation(u64 async_key);
void EndAsyncOperation();
SmcResult SmcGetResult(const SmcArguments &args);
SmcResult SmcGetResultData(const SmcArguments &args);
SmcResult SmcGetResult(SmcArguments &args);
SmcResult SmcGetResultData(SmcArguments &args);
}

4
exosphere2/program/source/smc/secmon_smc_rsa.cpp
View file

@ -19,12 +19,12 @@
namespace ams::secmon::smc {
SmcResult SmcModularExponentiate(const SmcArguments &args) {
SmcResult SmcModularExponentiate(SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
}
SmcResult SmcModularExponentiateByStorageKey(const SmcArguments &args) {
SmcResult SmcModularExponentiateByStorageKey(SmcArguments &args) {
/* TODO */
return SmcResult::NotImplemented;
}

4
exosphere2/program/source/smc/secmon_smc_rsa.hpp
View file

@ -19,7 +19,7 @@
namespace ams::secmon::smc {
SmcResult SmcModularExponentiate(const SmcArguments &args);
SmcResult SmcModularExponentiateByStorageKey(const SmcArguments &args);
SmcResult SmcModularExponentiate(SmcArguments &args);
SmcResult SmcModularExponentiateByStorageKey(SmcArguments &args);
}

214
libraries/libexosphere/include/exosphere/tegra/tegra_mc.hpp
View file

@ -17,17 +17,186 @@
#include <vapours.hpp>
#include <exosphere/reg.hpp>
#define MC_INTSTATUS (0x000)
#define MC_INTMASK (0x004)
#define MC_ERR_STATUS (0x008)
#define MC_ERR_ADR (0x00c)
#define MC_SMMU_CONFIG (0x010)
#define MC_INTSTATUS (0x000)
#define MC_INTMASK (0x004)
#define MC_ERR_STATUS (0x008)
#define MC_ERR_ADR (0x00C)
#define MC_SMMU_CONFIG (0x010)
#define MC_SMMU_PTB_ASID (0x01C)
#define MC_SMMU_PTB_DATA (0x020)
#define MC_SMMU_TLB_FLUSH (0x030)
#define MC_SMMU_PTC_FLUSH (0x034)
#define MC_EMEM_CFG (0x050)
#define MC_EMEM_ADR_CFG (0x054)
#define MC_EMEM_ARB_CFG (0x090)
#define MC_EMEM_ARB_OUTSTANDING_REQ (0x094)
#define MC_EMEM_ARB_TIMING_RCD (0x098)
#define MC_EMEM_ARB_TIMING_RP (0x09C)
#define MC_EMEM_ARB_TIMING_RC (0x0A0)
#define MC_EMEM_ARB_TIMING_RAS (0x0A4)
#define MC_EMEM_ARB_TIMING_FAW (0x0A8)
#define MC_EMEM_ARB_TIMING_RRD (0x0AC)
#define MC_EMEM_ARB_TIMING_RAP2PRE (0x0B0)
#define MC_EMEM_ARB_TIMING_WAP2PRE (0x0B4)
#define MC_EMEM_ARB_TIMING_R2R (0x0B8)
#define MC_EMEM_ARB_TIMING_W2W (0x0BC)
#define MC_EMEM_ARB_TIMING_R2W (0x0C0)
#define MC_EMEM_ARB_TIMING_W2R (0x0C4)
#define MC_EMEM_ARB_MISC2 (0x0C8)
#define MC_EMEM_ARB_DA_TURNS (0x0D0)
#define MC_EMEM_ARB_DA_COVERS (0x0D4)
#define MC_EMEM_ARB_MISC0 (0x0D8)
#define MC_EMEM_ARB_MISC1 (0x0DC)
#define MC_EMEM_ARB_RING1_THROTTLE (0x0E0)
#define MC_CLIENT_HOTRESET_CTRL (0x200)
#define MC_CLIENT_HOTRESET_STATUS (0x204)
#define MC_SMMU_AFI_ASID (0x238)
#define MC_SMMU_DC_ASID (0x240)
#define MC_SMMU_DCB_ASID (0x244)
#define MC_SMMU_HC_ASID (0x250)
#define MC_SMMU_HDA_ASID (0x254)
#define MC_SMMU_ISP2_ASID (0x258)
#define MC_SMMU_NVENC_ASID (0x264)
#define MC_SMMU_NV_ASID (0x268)
#define MC_SMMU_NV2_ASID (0x26C)
#define MC_SMMU_PPCS_ASID (0x270)
#define MC_SMMU_SATA_ASID (0x274)
#define MC_SMMU_VI_ASID (0x280)
#define MC_SMMU_VIC_ASID (0x284)
#define MC_SMMU_XUSB_HOST_ASID (0x288)
#define MC_SMMU_XUSB_DEV_ASID (0x28C)
#define MC_SMMU_TSEC_ASID (0x294)
#define MC_LATENCY_ALLOWANCE_AVPC_0 (0x2E4)
#define MC_LATENCY_ALLOWANCE_DC_0 (0x2E8)
#define MC_LATENCY_ALLOWANCE_DC_1 (0x2EC)
#define MC_LATENCY_ALLOWANCE_DCB_0 (0x2F4)
#define MC_LATENCY_ALLOWANCE_DCB_1 (0x2F8)
#define MC_LATENCY_ALLOWANCE_HC_0 (0x310)
#define MC_LATENCY_ALLOWANCE_HC_1 (0x314)
#define MC_LATENCY_ALLOWANCE_MPCORE_0 (0x320)
#define MC_LATENCY_ALLOWANCE_NVENC_0 (0x328)
#define MC_LATENCY_ALLOWANCE_PPCS_0 (0x344)
#define MC_LATENCY_ALLOWANCE_PPCS_1 (0x348)
#define MC_LATENCY_ALLOWANCE_ISP2_0 (0x370)
#define MC_LATENCY_ALLOWANCE_ISP2_1 (0x374)
#define MC_LATENCY_ALLOWANCE_XUSB_0 (0x37C)
#define MC_LATENCY_ALLOWANCE_XUSB_1 (0x380)
#define MC_LATENCY_ALLOWANCE_TSEC_0 (0x390)
#define MC_LATENCY_ALLOWANCE_VIC_0 (0x394)
#define MC_LATENCY_ALLOWANCE_VI2_0 (0x398)
#define MC_LATENCY_ALLOWANCE_GPU_0 (0x3AC)
#define MC_LATENCY_ALLOWANCE_SDMMCA_0 (0x3B8)
#define MC_LATENCY_ALLOWANCE_SDMMCAA_0 (0x3BC)
#define MC_LATENCY_ALLOWANCE_SDMMC_0 (0x3C0)
#define MC_LATENCY_ALLOWANCE_SDMMCAB_0 (0x3C4)
#define MC_LATENCY_ALLOWANCE_NVDEC_0 (0x3D8)
#define MC_LATENCY_ALLOWANCE_GPU2_0 (0x3E8)
#define MC_DIS_PTSA_RATE (0x41C)
#define MC_DIS_PTSA_MIN (0x420)
#define MC_DIS_PTSA_MAX (0x424)
#define MC_DISB_PTSA_RATE (0x428)
#define MC_DISB_PTSA_MIN (0x42C)
#define MC_DISB_PTSA_MAX (0x430)
#define MC_VE_PTSA_RATE (0x434)
#define MC_VE_PTSA_MIN (0x438)
#define MC_VE_PTSA_MAX (0x43C)
#define MC_MLL_MPCORER_PTSA_RATE (0x44C)
#define MC_RING1_PTSA_RATE (0x47C)
#define MC_RING1_PTSA_MIN (0x480)
#define MC_RING1_PTSA_MAX (0x484)
#define MC_PCX_PTSA_RATE (0x4AC)
#define MC_PCX_PTSA_MIN (0x4B0)
#define MC_PCX_PTSA_MAX (0x4B4)
#define MC_MSE_PTSA_RATE (0x4C4)
#define MC_MSE_PTSA_MIN (0x4C8)
#define MC_MSE_PTSA_MAX (0x4CC)
#define MC_AHB_PTSA_RATE (0x4DC)
#define MC_AHB_PTSA_MIN (0x4E0)
#define MC_AHB_PTSA_MAX (0x4E4)
#define MC_APB_PTSA_RATE (0x4E8)
#define MC_APB_PTSA_MIN (0x4EC)
#define MC_APB_PTSA_MAX (0x4F0)
#define MC_FTOP_PTSA_RATE (0x50C)
#define MC_HOST_PTSA_RATE (0x518)
#define MC_HOST_PTSA_MIN (0x51C)
#define MC_HOST_PTSA_MAX (0x520)
#define MC_USBX_PTSA_RATE (0x524)
#define MC_USBX_PTSA_MIN (0x528)
#define MC_USBX_PTSA_MAX (0x52C)
#define MC_USBD_PTSA_RATE (0x530)
#define MC_USBD_PTSA_MIN (0x534)
#define MC_USBD_PTSA_MAX (0x538)
#define MC_GK_PTSA_RATE (0x53C)
#define MC_GK_PTSA_MIN (0x540)
#define MC_GK_PTSA_MAX (0x544)
#define MC_AUD_PTSA_RATE (0x548)
#define MC_AUD_PTSA_MIN (0x54C)
#define MC_AUD_PTSA_MAX (0x550)
#define MC_VICPC_PTSA_RATE (0x554)
#define MC_VICPC_PTSA_MIN (0x558)
#define MC_VICPC_PTSA_MAX (0x55C)
#define MC_JPG_PTSA_RATE (0x584)
#define MC_JPG_PTSA_MIN (0x588)
#define MC_JPG_PTSA_MAX (0x58C)
#define MC_GK2_PTSA_RATE (0x610)
#define MC_GK2_PTSA_MIN (0x614)
#define MC_GK2_PTSA_MAX (0x618)
#define MC_SDM_PTSA_RATE (0x61C)
#define MC_SDM_PTSA_MIN (0x620)
#define MC_SDM_PTSA_MAX (0x624)
#define MC_HDAPC_PTSA_RATE (0x628)
#define MC_HDAPC_PTSA_MIN (0x62C)
#define MC_HDAPC_PTSA_MAX (0x630)
#define MC_SEC_CARVEOUT_BOM (0x670)
#define MC_SEC_CARVEOUT_SIZE_MB (0x674)
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A (0x690)
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB (0x694)
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B (0x698)
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB (0x69C)
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C (0x6A0)
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB (0x6A4)
#define MC_EMEM_ARB_TIMING_RFCPB (0x6C0)
#define MC_EMEM_ARB_TIMING_CCDMW (0x6C4)
#define MC_EMEM_ARB_REFPB_HP_CTRL (0x6F0)
#define MC_EMEM_ARB_REFPB_BANK_CTRL (0x6F4)
#define MC_PTSA_GRANT_DECREMENT (0x960)
#define MC_CLIENT_HOTRESET_CTRL_1 (0x970)
#define MC_CLIENT_HOTRESET_STATUS_1 (0x974)
#define MC_SMMU_PTC_FLUSH_1 (0x9B8)
#define MC_SMMU_DC1_ASID (0xA88)
#define MC_SMMU_SDMMC1A_ASID (0xA94)
#define MC_SMMU_SDMMC2A_ASID (0xA98)
#define MC_SMMU_SDMMC3A_ASID (0xA9C)
#define MC_SMMU_SDMMC4A_ASID (0xAA0)
#define MC_SMMU_ISP2B_ASID (0xAA4)
#define MC_SMMU_GPU_ASID (0xAA8)
#define MC_SMMU_GPUB_ASID (0xAAC)
#define MC_SMMU_PPCS2_ASID (0xAB0)
#define MC_SMMU_NVDEC_ASID (0xAB4)
#define MC_SMMU_APE_ASID (0xAB8)
#define MC_SMMU_SE_ASID (0xABC)
#define MC_SMMU_NVJPG_ASID (0xAC0)
#define MC_SMMU_HC1_ASID (0xAC4)
#define MC_SMMU_SE1_ASID (0xAC8)
#define MC_SMMU_AXIAP_ASID (0xACC)
#define MC_SMMU_ETR_ASID (0xAD0)
#define MC_SMMU_TSECB_ASID (0xAD4)
#define MC_SMMU_TSEC1_ASID (0xAD8)
#define MC_SMMU_TSECB1_ASID (0xADC)
#define MC_SMMU_NVDEC1_ASID (0xAE0)
#define MC_EMEM_ARB_DHYST_CTRL (0xBCC)
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0 (0xBD0)
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1 (0xBD4)
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2 (0xBD8)
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3 (0xBDC)
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4 (0xBE0)
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5 (0xBE4)
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6 (0xBE8)
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7 (0xBEC)
#define MC_ERR_GENERALIZED_CARVEOUT_STATUS (0xC00)
#define MC_SMMU_TLB_CONFIG (0x014)
#define MC_SMMU_PTC_CONFIG (0x018)
#define MC_SMMU_PTB_ASID (0x01c)
#define MC_SMMU_PTB_DATA (0x020)
#define MC_SMMU_TLB_FLUSH (0x030)
#define MC_SMMU_PTC_FLUSH (0x034)
#define MC_SMMU_AVPC_ASID (0x23C)
#define MC_SMMU_PPCS1_ASID (0x298)
@ -145,6 +314,33 @@
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3 (0xd78)
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4 (0xd7c)
#define MC_STAT_CONTROL (0x100)
#define MC_STAT_EMC_CLOCK_LIMIT (0x108)
#define MC_STAT_EMC_CLOCK_LIMIT_MSBS (0x10c)
#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_LO (0x118)
#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_HI (0x11c)
#define MC_STAT_EMC_FILTER_SET0_SPARE (0x124)
#define MC_STAT_EMC_FILTER_SET0_CLIENT_0 (0x128)
#define MC_STAT_EMC_FILTER_SET0_CLIENT_1 (0x12c)
#define MC_STAT_EMC_FILTER_SET0_CLIENT_2 (0x130)
#define MC_STAT_EMC_FILTER_SET0_CLIENT_3 (0x134)
#define MC_STAT_EMC_SET0_COUNT (0x138)
#define MC_STAT_EMC_SET0_COUNT_MSBS (0x13c)
#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_LO (0x158)
#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_HI (0x15c)
#define MC_STAT_EMC_FILTER_SET1_SPARE (0x164)
#define MC_STAT_EMC_FILTER_SET1_CLIENT_0 (0x168)
#define MC_STAT_EMC_FILTER_SET1_CLIENT_1 (0x16c)
#define MC_STAT_EMC_FILTER_SET1_CLIENT_2 (0x170)
#define MC_STAT_EMC_FILTER_SET1_CLIENT_3 (0x174)
#define MC_STAT_EMC_SET1_COUNT (0x178)
#define MC_STAT_EMC_SET1_COUNT_MSBS (0x17c)
#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_UPPER (0xa20)
#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_UPPER (0xa24)
#define MC_STAT_EMC_FILTER_SET0_CLIENT_4 (0xb88)
#define MC_STAT_EMC_FILTER_SET1_CLIENT_4 (0xb8c)
#define MC_STAT_EMC_FILTER_SET0_CLIENT_5 (0xbc4)
#define MC_STAT_EMC_FILTER_SET1_CLIENT_5 (0xbc8)
#define MC_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (MC, NAME)
#define MC_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (MC, NAME, VALUE)

155
libraries/libexosphere/include/exosphere/tegra/tegra_pmc.hpp
View file

@ -17,72 +17,95 @@
#include <vapours.hpp>
#include <exosphere/reg.hpp>
#define APBDEV_PMC_CNTRL (0x000)
#define APBDEV_PMC_DPD_SAMPLE (0x020)
#define APBDEV_PMC_DPD_ENABLE (0x024)
#define APBDEV_PMC_CLAMP_STATUS (0x02C)
#define APBDEV_PMC_PWRGATE_TOGGLE (0x030)
#define APBDEV_PMC_PWRGATE_STATUS (0x038)
#define APBDEV_PMC_SCRATCH0 (0x050)
#define APBDEV_PMC_SCRATCH1 (0x054)
#define APBDEV_PMC_SCRATCH12 (0x080)
#define APBDEV_PMC_SCRATCH13 (0x084)
#define APBDEV_PMC_SCRATCH18 (0x098)
#define APBDEV_PMC_SCRATCH20 (0x0A0)
#define APBDEV_PMC_CRYPTO_OP (0x0F4)
#define APBDEV_PM (0x014)
#define APBDEV_PMC_WAKE2_STATUS (0x168)
#define APBDEV_PMC_WEAK_BIAS (0x2C8)
#define APBDEV_PMC_CNTRL2 (0x440)
#define APBDEV_PMC_FUSE_CTRL (0x450)
#define APBDEV_PMC_IO_DPD3_REQ (0x45C)
#define APBDEV_PMC_IO_DPD3_STATUS (0x460)
#define APBDEV_PMC_IO_DPD4_REQ (0x464)
#define APBDEV_PMC_IO_DPD4_STATUS (0x468)
#define APBDEV_PMC_SET_SW_CLAMP (0x47C)
#define APBDEV_PMC_DDR_CNTRL (0x4E4)
#define APBDEV_PMC_SEC_DISABLE (0x004)
#define APBDEV_PMC_SEC_DISABLE2 (0x2C4)
#define APBDEV_PMC_SEC_DISABLE3 (0x2D8)
#define APBDEV_PMC_SEC_DISABLE4 (0x5B0)
#define APBDEV_PMC_SEC_DISABLE5 (0x5B4)
#define APBDEV_PMC_SEC_DISABLE6 (0x5B8)
#define APBDEV_PMC_SEC_DISABLE7 (0x5BC)
#define APBDEV_PMC_SEC_DISABLE8 (0x5C0)
#define APBDEV_PMC_SCRATCH43 (0x22C)
#define APBDEV_PMC_SCRATCH190 (0x818)
#define APBDEV_PMC_SCRATCH200 (0x840)
#define APBDEV_PMC_SEC_DISABLE3 (0x2D8)
#define APBDEV_PMC_SECURE_SCRATCH4 (0x0C0)
#define APBDEV_PMC_SECURE_SCRATCH5 (0x0C4)
#define APBDEV_PMC_SECURE_SCRATCH6 (0x224)
#define APBDEV_PMC_SECURE_SCRATCH7 (0x228)
#define APBDEV_PMC_SECURE_SCRATCH16 (0x320)
#define APBDEV_PMC_SECURE_SCRATCH21 (0x334)
#define APBDEV_PMC_SECURE_SCRATCH24 (0x340)
#define APBDEV_PMC_SECURE_SCRATCH25 (0x344)
#define APBDEV_PMC_SECURE_SCRATCH26 (0x348)
#define APBDEV_PMC_SECURE_SCRATCH27 (0x34C)
#define APBDEV_PMC_SECURE_SCRATCH32 (0x360)
#define APBDEV_PMC_SECURE_SCRATCH34 (0x368)
#define APBDEV_PMC_SECURE_SCRATCH35 (0x36C)
#define APBDEV_PMC_SECURE_SCRATCH39 (0x37C)
#define APBDEV_PMC_SECURE_SCRATCH51 (0x3AC)
#define APBDEV_PMC_SECURE_SCRATCH55 (0x3BC)
#define APBDEV_PMC_SECURE_SCRATCH74 (0x408)
#define APBDEV_PMC_SECURE_SCRATCH75 (0x40C)
#define APBDEV_PMC_SECURE_SCRATCH76 (0x410)
#define APBDEV_PMC_SECURE_SCRATCH77 (0x414)
#define APBDEV_PMC_SECURE_SCRATCH78 (0x418)
#define APBDEV_PMC_SECURE_SCRATCH99 (0xAE4)
#define APBDEV_PMC_SECURE_SCRATCH100 (0xAE8)
#define APBDEV_PMC_SECURE_SCRATCH101 (0xAEC)
#define APBDEV_PMC_SECURE_SCRATCH102 (0xAF0)
#define APBDEV_PMC_SECURE_SCRATCH103 (0xAF4)
#define APBDEV_PMC_SECURE_SCRATCH112 (0xB18)
#define APBDEV_PMC_SECURE_SCRATCH113 (0xB1C)
#define APBDEV_PMC_SECURE_SCRATCH114 (0xB20)
#define APBDEV_PMC_SECURE_SCRATCH115 (0xB24)
#define APBDEV_PMC_CNTRL (0x000)
#define APBDEV_PMC_WAKE_MASK (0x00C)
#define APBDEV_PMC_WAKE_LVL (0x010)
#define APBDEV_PMC_WAKE_STATUS (0x014)
#define APBDEV_PMC_DPD_PADS_ORIDE (0x01C)
#define APBDEV_PMC_DPD_SAMPLE (0x020)
#define APBDEV_PMC_DPD_ENABLE (0x024)
#define APBDEV_PMC_CLAMP_STATUS (0x02C)
#define APBDEV_PMC_PWRGATE_TOGGLE (0x030)
#define APBDEV_PMC_REMOVE_CLAMPING_CMD (0x034)
#define APBDEV_PMC_PWRGATE_STATUS (0x038)
#define APBDEV_PMC_PWRGOOD_TIMER (0x03C)
#define APBDEV_PMC_BLINK_TIMER (0x040)
#define APBDEV_PMC_NO_IOPOWER (0x044)
#define APBDEV_PMC_PWR_DET (0x048)
#define APBDEV_PMC_SCRATCH0 (0x050)
#define APBDEV_PMC_SCRATCH1 (0x054)
#define APBDEV_PMC_SCRATCH12 (0x080)
#define APBDEV_PMC_SCRATCH13 (0x084)
#define APBDEV_PMC_SCRATCH18 (0x098)
#define APBDEV_PMC_SCRATCH20 (0x0A0)
#define APBDEV_PMC_AUTO_WAKE_LVL_MASK (0x0DC)
#define APBDEV_PMC_WAKE_DELAY (0x0E0)
#define APBDEV_PMC_PWR_DET_VAL (0x0E4)
#define APBDEV_PMC_CRYPTO_OP (0x0F4)
#define APBDEV_PMC_WAKE2_MASK (0x160)
#define APBDEV_PMC_WAKE2_LVL (0x164)
#define APBDEV_PMC_WAKE2_STATUS (0x168)
#define APBDEV_PMC_AUTO_WAKE2_LVL_MASK (0x170)
#define APBDEV_PMC_CLK_OUT_CNTRL (0x1A8)
#define APBDEV_PMC_IO_DPD_REQ (0x1B8)
#define APBDEV_PMC_IO_DPD_STATUS (0x1BC)
#define APBDEV_PMC_IO_DPD2_REQ (0x1C0)
#define APBDEV_PMC_IO_DPD2_STATUS (0x1C4)
#define APBDEV_PMC_SEL_DPD_TIM (0x1C8)
#define APBDEV_PMC_TSC_MULT (0x2B4)
#define APBDEV_PMC_WEAK_BIAS (0x2C8)
#define APBDEV_PMC_GPU_RG_CNTRL (0x2D4)
#define APBDEV_PMC_CNTRL2 (0x440)
#define APBDEV_PMC_FUSE_CTRL (0x450)
#define APBDEV_PMC_IO_DPD3_REQ (0x45C)
#define APBDEV_PMC_IO_DPD3_STATUS (0x460)
#define APBDEV_PMC_IO_DPD4_REQ (0x464)
#define APBDEV_PMC_IO_DPD4_STATUS (0x468)
#define APBDEV_PMC_SET_SW_CLAMP (0x47C)
#define APBDEV_PMC_WAKE_DEBOUNCE_EN (0x4D8)
#define APBDEV_PMC_DDR_CNTRL (0x4E4)
#define APBDEV_PMC_SEC_DISABLE (0x004)
#define APBDEV_PMC_SEC_DISABLE2 (0x2C4)
#define APBDEV_PMC_SEC_DISABLE3 (0x2D8)
#define APBDEV_PMC_SEC_DISABLE4 (0x5B0)
#define APBDEV_PMC_SEC_DISABLE5 (0x5B4)
#define APBDEV_PMC_SEC_DISABLE6 (0x5B8)
#define APBDEV_PMC_SEC_DISABLE7 (0x5BC)
#define APBDEV_PMC_SEC_DISABLE8 (0x5C0)
#define APBDEV_PMC_SCRATCH43 (0x22C)
#define APBDEV_PMC_SCRATCH190 (0x818)
#define APBDEV_PMC_SCRATCH200 (0x840)
#define APBDEV_PMC_SEC_DISABLE3 (0x2D8)
#define APBDEV_PMC_SECURE_SCRATCH4 (0x0C0)
#define APBDEV_PMC_SECURE_SCRATCH5 (0x0C4)
#define APBDEV_PMC_SECURE_SCRATCH6 (0x224)
#define APBDEV_PMC_SECURE_SCRATCH7 (0x228)
#define APBDEV_PMC_SECURE_SCRATCH16 (0x320)
#define APBDEV_PMC_SECURE_SCRATCH21 (0x334)
#define APBDEV_PMC_SECURE_SCRATCH24 (0x340)
#define APBDEV_PMC_SECURE_SCRATCH25 (0x344)
#define APBDEV_PMC_SECURE_SCRATCH26 (0x348)
#define APBDEV_PMC_SECURE_SCRATCH27 (0x34C)
#define APBDEV_PMC_SECURE_SCRATCH32 (0x360)
#define APBDEV_PMC_SECURE_SCRATCH34 (0x368)
#define APBDEV_PMC_SECURE_SCRATCH35 (0x36C)
#define APBDEV_PMC_SECURE_SCRATCH39 (0x37C)
#define APBDEV_PMC_SECURE_SCRATCH51 (0x3AC)
#define APBDEV_PMC_SECURE_SCRATCH55 (0x3BC)
#define APBDEV_PMC_SECURE_SCRATCH74 (0x408)
#define APBDEV_PMC_SECURE_SCRATCH75 (0x40C)
#define APBDEV_PMC_SECURE_SCRATCH76 (0x410)
#define APBDEV_PMC_SECURE_SCRATCH77 (0x414)
#define APBDEV_PMC_SECURE_SCRATCH78 (0x418)
#define APBDEV_PMC_SECURE_SCRATCH99 (0xAE4)
#define APBDEV_PMC_SECURE_SCRATCH100 (0xAE8)
#define APBDEV_PMC_SECURE_SCRATCH101 (0xAEC)
#define APBDEV_PMC_SECURE_SCRATCH102 (0xAF0)
#define APBDEV_PMC_SECURE_SCRATCH103 (0xAF4)
#define APBDEV_PMC_SECURE_SCRATCH112 (0xB18)
#define APBDEV_PMC_SECURE_SCRATCH113 (0xB1C)
#define APBDEV_PMC_SECURE_SCRATCH114 (0xB20)
#define APBDEV_PMC_SECURE_SCRATCH115 (0xB24)
#define PMC_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (APBDEV_PMC, NAME)