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Fix exception handlers (thanks @fincs)
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parent
43d1816ac2
commit
ea2693dd2d
2 changed files with 10 additions and 9 deletions
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@ -37,10 +37,11 @@ void exception_handler_main(uint32_t *registers, unsigned int exception_type) {
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uint32_t instr_addr = pc + ((cpsr & 0x20) ? 2 : 4) - CODE_DUMP_SIZE;
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code_dump_size =0;// safecpy(code_dump, (const void *)instr_addr, CODE_DUMP_SIZE);
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stack_dump_size = safecpy(stack_dump, (const void *)registers[14], STACK_DUMP_SIZE);
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printk("Something went wrong...\n");
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code_dump_size = safecpy(code_dump, (const void *)instr_addr, CODE_DUMP_SIZE);
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stack_dump_size = safecpy(stack_dump, (const void *)registers[13], STACK_DUMP_SIZE);
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printk("\nException type: %s\n", exception_names[exception_type]);
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printk("\nRegisters:\n\n");
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@ -55,6 +56,7 @@ void exception_handler_main(uint32_t *registers, unsigned int exception_type) {
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printk("\nCode dump:\n");
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hexdump(code_dump, code_dump_size, instr_addr);
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printk("\nStack dump:\n");
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hexdump(stack_dump, stack_dump_size, registers[14]);
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hexdump(stack_dump, stack_dump_size, registers[13]);
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printk("\n");
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fatal_error("An exception occured!\n");
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}
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@ -55,12 +55,10 @@ _exception_handler_data_abort:
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/* Mask interrupts (abort mode). */
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msr cpsr_cx, #0xD7
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adr sp, safecpy
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add sp, sp, #8
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adr sp, safecpy+8
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cmp lr, sp
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blo _exception_handler_data_abort_normal
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adr sp, _safecpy_end
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add sp, sp, #8
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adr sp, _safecpy_end+8
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cmp lr, sp
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bhs _exception_handler_data_abort_normal
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@ -87,7 +85,8 @@ safecpy:
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_safecpy_loop_end:
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mov r0, r3
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pop {r4, pc}
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pop {r4, lr}
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bx lr /* Need to do that separately on ARMv4. */
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_safecpy_end:
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