From edf2bbc30ee85913e0273752cb94ae89140e8e30 Mon Sep 17 00:00:00 2001
From: TuxSH <1922548+TuxSH@users.noreply.github.com>
Date: Mon, 3 Feb 2020 01:32:32 +0000
Subject: [PATCH] thermosphere: I wish ld wasn't dumb (also, bugfix). This
 saves 4K

---
 thermosphere/src/platform/qemu/stage2_config.c  | 4 ++--
 thermosphere/src/platform/tegra/stage2_config.c | 5 ++---
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/thermosphere/src/platform/qemu/stage2_config.c b/thermosphere/src/platform/qemu/stage2_config.c
index bbd60a6d3..8f8ce6060 100644
--- a/thermosphere/src/platform/qemu/stage2_config.c
+++ b/thermosphere/src/platform/qemu/stage2_config.c
@@ -28,7 +28,6 @@
 static TEMPORARY ALIGN(0x1000) u64 g_vttbl[BIT(ADDRSPACESZ2 - 30)] = {0};
 static TEMPORARY ALIGN(0x1000) u64 g_vttbl_l2_mmio_0_0[512] = {0};
 static TEMPORARY ALIGN(0x1000) u64 g_vttbl_l3_0[512] = {0};
-static TEMPORARY uintptr_t g_vttblPaddr;
 
 static inline void identityMapL1(u64 *tbl, uintptr_t addr, size_t size, u64 attribs)
 {
@@ -51,8 +50,9 @@ uintptr_t stage2Configure(u32 *addrSpaceSize)
     static const u64 devattrs = 0 | MMU_S2AP_RW | MMU_MEMATTR_DEVICE_NGNRE;
     static const u64 unchanged = MMU_S2AP_RW | MMU_MEMATTR_NORMAL_CACHEABLE_OR_UNCHANGED;
 
+    uintptr_t g_vttblPaddr = va2pa(g_vttbl);
+
     if (currentCoreCtx->isBootCore) {
-        g_vttblPaddr = va2pa(g_vttbl);
         uintptr_t *l2pa = (uintptr_t *)va2pa(g_vttbl_l2_mmio_0_0);
         uintptr_t *l3pa = (uintptr_t *)va2pa(g_vttbl_l3_0);
 
diff --git a/thermosphere/src/platform/tegra/stage2_config.c b/thermosphere/src/platform/tegra/stage2_config.c
index 2ca41ccdf..b27ba2d0d 100644
--- a/thermosphere/src/platform/tegra/stage2_config.c
+++ b/thermosphere/src/platform/tegra/stage2_config.c
@@ -26,7 +26,6 @@
 static TEMPORARY ALIGN(0x1000) u64 g_vttbl[BIT(ADDRSPACESZ2 - 30)] = {0};
 static TEMPORARY ALIGN(0x1000) u64 g_vttbl_l2_mmio_0[512] = {0};
 static TEMPORARY ALIGN(0x1000) u64 g_vttbl_l3_0[512] = {0};
-static TEMPORARY uintptr_t g_vttblPaddr;
 
 static inline void identityMapL1(u64 *tbl, uintptr_t addr, size_t size, u64 attribs)
 {
@@ -48,8 +47,8 @@ uintptr_t stage2Configure(u32 *addrSpaceSize)
     *addrSpaceSize = ADDRSPACESZ2;
     static const u64 devattrs = MMU_PTE_BLOCK_XN | MMU_S2AP_RW | MMU_MEMATTR_DEVICE_NGNRE;
     static const u64 unchanged = MMU_S2AP_RW | MMU_MEMATTR_NORMAL_CACHEABLE_OR_UNCHANGED;
+    uintptr_t g_vttblPaddr = va2pa(g_vttbl);
     if (currentCoreCtx->isBootCore) {
-        g_vttblPaddr = va2pa(g_vttbl);
         uintptr_t *l2pa = (uintptr_t *)va2pa(g_vttbl_l2_mmio_0);
         uintptr_t *l3pa = (uintptr_t *)va2pa(g_vttbl_l3_0);
 
@@ -69,5 +68,5 @@ uintptr_t stage2Configure(u32 *addrSpaceSize)
         mmu_map_page_range(g_vttbl_l3_0, MEMORY_MAP_PA_GICC, MEMORY_MAP_PA_GICD, 0x2000ull, devattrs);
     }
 
-    return (uintptr_t)g_vttbl;
+    return g_vttblPaddr;
 }