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3152 commits

Author SHA1 Message Date
TuxSH
f23fb45956 thermosphere: copy paste lots of gdb luma files (but don't build them yet) 2021-02-19 21:51:51 +00:00
TuxSH
61fec56c6e thermosphere: minor changes 2021-02-19 21:51:51 +00:00
TuxSH
a665f49b93 thermosphere: incl pattern utils 2021-02-19 21:51:51 +00:00
TuxSH
3e8bd764d5 thermosphere: unfuck sw breakpoint logic 2021-02-19 21:51:51 +00:00
TuxSH
c64ccd86ee thermosphere: uninline recursive lock funcs 2021-02-19 21:51:50 +00:00
TuxSH
217c1ad054 thermosphere: implement reading and writing guest memory 2021-02-19 21:51:50 +00:00
TuxSH
0f0228e240 thermosphere: we expose a GICv2, not a GICv1 2021-02-19 21:51:49 +00:00
TuxSH
3ca3e094fe thermosphere: use ish instead of sy in most places 2021-02-19 21:51:49 +00:00
TuxSH
d1cd17a9df thermosphere: fix fmt.c "l" handling 2021-02-19 21:51:49 +00:00
TuxSH
626f0ecb98 thermosphere: major refactor of memory map
- use recursive stage 1 page table (thanks @fincs for this idea)
- NULL now unmapped
- no identity mapping
- image + GICv2 now mapped at the same address for every platform
- tempbss mapped just after "real" bss, can now steal unused mem from
the latter
- no hardcoded VAs for other MMIO devices
- tegra: remove timers, use the generic timer instead
2021-02-19 21:51:48 +00:00
TuxSH
92a291cd41 thermosphere: disable interrupts in debugPauseCores 2021-02-19 21:51:48 +00:00
TuxSH
906d6a4f20 thermosphere: rewrite debug pause & fix single step state machine 2021-02-19 21:51:48 +00:00
TuxSH
6b8a843ffb thermosphere: trap set/way dcache access
note: qemu does not implement the trap
2021-02-19 21:51:47 +00:00
TuxSH
72d1992eec thermosphere: use barriers and caches *properly*. Cache code refactoring
- set/way cache ops create losses of coherency, do not broadcast and are only meant to be used on boot, period.

Cache ops by VA are **the only way** to do data cache maintenance.

Fix a bug where the L2 cache was evicted by each core. It shouldn't have.

- Cleaning dcache to PoU and invalidating icache to PoU, by VA is sufficient for self-modifying code

- Since we operate within a single cluster and don't do DMA, we almost always operate within the inner shareability domain

(commit untested on real hw)
2021-02-19 21:51:47 +00:00
TuxSH
1369697058 thermosphere: add debug pause logic 2021-02-19 21:51:47 +00:00
TuxSH
b6a130547a thermosphere: add common asm macros 2021-02-19 21:51:46 +00:00
TuxSH
067770334e thermosphere: add fpu regs save/restore 2021-02-19 21:51:46 +00:00
TuxSH
a7741c8576 thermosphere: add cctx->userFrame 2021-02-19 21:51:46 +00:00
TuxSH
dd96c8b32b thermosphere: fix ptimer time freezing (again) 2021-02-19 21:51:45 +00:00
TuxSH
68a1ce6dd2 thermosphere: properly implement guest timer stuff 2021-02-19 21:51:45 +00:00
TuxSH
388c245ce4 thermosphere: add TransportInterface abstraction layer 2021-02-19 21:51:45 +00:00
TuxSH
1086c0612c thermosphere: refactor tegra uart code, etc. 2021-02-19 21:51:44 +00:00
TuxSH
8dc9be9f8e thermosphere: pl011 uart refactor 2021-02-19 21:51:44 +00:00
TuxSH
018260645a thermosphere: fix pl101 uart reg definitions 2021-02-19 21:51:44 +00:00
TuxSH
a6d191bf4b thermosphere: add proper memory/instruction barriers for breakpoint stuff 2021-02-19 21:51:43 +00:00
TuxSH
1eb60a2a52 thermosphere: add hypervisor timer code 2021-02-19 21:51:43 +00:00
TuxSH
3d3a9925b9 thermosphere: qemu: get rid of arm tf
qemu impls psci anyway
2021-02-19 21:51:42 +00:00
TuxSH
501472324f thermosphere: refactor exception handlers & add stolen time/emulated ptimer logic 2021-02-19 21:51:42 +00:00
TuxSH
b9d07fccd6 thermosphere: rewrite sysreg trapping code, add skeleton code for timer val trap handling; support A32 EL1 once again 2021-02-19 21:51:42 +00:00
TuxSH
d42d9e60b9 thermosphere: don't trap memory register writes/don't migrate sw breakpoints
Makes no sense on a system with ASLR
2021-02-19 21:51:41 +00:00
TuxSH
28552da099 thermosphere: vgic: largely reduce the number of mmio accesses
since we have to use 64 bits for VirqState anyway
2021-02-19 21:51:41 +00:00
TuxSH
d56185e432 thermosphere: make the pending virq list ordering stable 2021-02-19 21:51:41 +00:00
TuxSH
c42aef6ba7 thermosphere: fix wrong icfgr shift; fix list handling bug 2021-02-19 21:51:40 +00:00
TuxSH
03fe744bc4 thermosphere: vgic: fix OOB accesses, fix icfgr and itargetsr handling
qemu actually allows SPIs to use the N-N model
2021-02-19 21:51:40 +00:00
TuxSH
e49a035455 thermosphere: fix is/ic registers usage; fix offset calculation 2021-02-19 21:51:40 +00:00
TuxSH
0811572889 thermosphere: fix truncation in vgicCleanupPendingList 2021-02-19 21:51:39 +00:00
TuxSH
76a5e745e4 thermosphere: honor irq config for ppis 2021-02-19 21:51:39 +00:00
TuxSH
7130b6efd1 thermosphere: yikes 2021-02-19 21:51:39 +00:00
TuxSH
37b14bc4b8 thermosphere: use strict volatile bitfields just in case 2021-02-19 21:51:38 +00:00
TuxSH
13174e7458 thermosphere: vgic: fix critical bug in vgicUpdateState, add more checks
Yikes.
2021-02-19 21:51:38 +00:00
TuxSH
ef79908594 thermosphere: add CFI where needed, add PANIC macro, etc. 2021-02-19 21:51:38 +00:00
TuxSH
3a13ab2e46 thermosphere: vgic: mostly fix vSGI handling, remove unimplementable/unused stuff + bugfixes
Still somewhat broken, though
2021-02-19 21:51:37 +00:00
TuxSH
676a895cca thermosphere: fix guest access to irq 25, etc; we don't need to raise VI manually
See Armv8a TRM "Virtual IRQ exception"
2021-02-19 21:51:37 +00:00
TuxSH
cdf3bc6942 thermosphere: add PPI definitions 2021-02-19 21:51:37 +00:00
TuxSH
fe0662a75d vgic: fix multiple bugs 2021-02-19 21:51:36 +00:00
TuxSH
f3ad62d1b8 thermosphere: fix various vgic bugs; fix register access OOB bug (xzr) 2021-02-19 21:51:36 +00:00
TuxSH
27859a7541 thermosphere: vgic: fix enabled state of virqs 2021-02-19 21:51:36 +00:00
TuxSH
e3b6d64f1b thermosphere: fix multiple bugs 2021-02-19 21:51:35 +00:00
TuxSH
c17b81aaf6 thermosphere: vgic code draft 2021-02-19 21:51:35 +00:00
TuxSH
176be2386d thermosphere: also trap GICH (to deny access) 2021-02-19 21:51:35 +00:00