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15 commits

Author SHA1 Message Date
TuxSH
8dc9be9f8e thermosphere: pl011 uart refactor 2021-02-19 21:51:44 +00:00
TuxSH
1eb60a2a52 thermosphere: add hypervisor timer code 2021-02-19 21:51:43 +00:00
TuxSH
501472324f thermosphere: refactor exception handlers & add stolen time/emulated ptimer logic 2021-02-19 21:51:42 +00:00
TuxSH
d42d9e60b9 thermosphere: don't trap memory register writes/don't migrate sw breakpoints
Makes no sense on a system with ASLR
2021-02-19 21:51:41 +00:00
TuxSH
28552da099 thermosphere: vgic: largely reduce the number of mmio accesses
since we have to use 64 bits for VirqState anyway
2021-02-19 21:51:41 +00:00
TuxSH
c42aef6ba7 thermosphere: fix wrong icfgr shift; fix list handling bug 2021-02-19 21:51:40 +00:00
TuxSH
03fe744bc4 thermosphere: vgic: fix OOB accesses, fix icfgr and itargetsr handling
qemu actually allows SPIs to use the N-N model
2021-02-19 21:51:40 +00:00
TuxSH
e49a035455 thermosphere: fix is/ic registers usage; fix offset calculation 2021-02-19 21:51:40 +00:00
TuxSH
3a13ab2e46 thermosphere: vgic: mostly fix vSGI handling, remove unimplementable/unused stuff + bugfixes
Still somewhat broken, though
2021-02-19 21:51:37 +00:00
TuxSH
676a895cca thermosphere: fix guest access to irq 25, etc; we don't need to raise VI manually
See Armv8a TRM "Virtual IRQ exception"
2021-02-19 21:51:37 +00:00
TuxSH
e3b6d64f1b thermosphere: fix multiple bugs 2021-02-19 21:51:35 +00:00
TuxSH
c17b81aaf6 thermosphere: vgic code draft 2021-02-19 21:51:35 +00:00
TuxSH
b2c5ef2611 thermopshere: add "execute function" sgi 2021-02-19 21:51:34 +00:00
TuxSH
0b69407f8e thermosphere: barrier & active core mask 2021-02-19 21:51:33 +00:00
TuxSH
0a9a8c2f15 thermosphere: handle physical IRQs 2021-02-19 21:51:33 +00:00