mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-11-05 19:51:45 +00:00
243 lines
7 KiB
C
243 lines
7 KiB
C
#include <string.h>
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#include "car.h"
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#include "fuse.h"
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#include "utils.h"
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#include "timers.h"
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#include "exocfg.h"
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#include "masterkey.h"
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/* Prototypes for internal commands. */
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void fuse_make_regs_visible(void);
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void fuse_enable_power(void);
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void fuse_disable_power(void);
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void fuse_wait_idle(void);
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/* Initialize the FUSE driver */
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void fuse_init(void)
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{
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fuse_make_regs_visible();
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fuse_secondary_private_key_disable();
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fuse_disable_programming();
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/* TODO: Overrides (iROM patches) and various reads happen here */
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}
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/* Make all fuse registers visible */
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void fuse_make_regs_visible(void)
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{
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CLK_RST_CONTROLLER_MISC_CLK_ENB_0 |= BIT(28);
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}
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/* Enable power to the fuse hardware array */
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void fuse_enable_power(void)
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{
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FUSE_REGS->FUSE_PWR_GOOD_SW = 1;
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wait(1);
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}
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/* Disable power to the fuse hardware array */
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void fuse_disable_power(void)
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{
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FUSE_REGS->FUSE_PWR_GOOD_SW = 0;
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wait(1);
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}
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/* Wait for the fuse driver to go idle */
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void fuse_wait_idle(void)
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{
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uint32_t ctrl_val = 0;
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/* Wait for STATE_IDLE */
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while ((ctrl_val & (0xF0000)) != 0x40000)
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{
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wait(1);
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ctrl_val = FUSE_REGS->FUSE_CTRL;
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}
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}
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/* Read a fuse from the hardware array */
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uint32_t fuse_hw_read(uint32_t addr)
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{
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fuse_wait_idle();
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/* Program the target address */
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FUSE_REGS->FUSE_REG_ADDR = addr;
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/* Enable read operation in control register */
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uint32_t ctrl_val = FUSE_REGS->FUSE_CTRL;
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ctrl_val &= ~0x3;
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ctrl_val |= 0x1; /* Set FUSE_READ command */
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FUSE_REGS->FUSE_CTRL = ctrl_val;
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fuse_wait_idle();
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return FUSE_REGS->FUSE_REG_READ;
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}
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/* Write a fuse in the hardware array */
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void fuse_hw_write(uint32_t value, uint32_t addr)
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{
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fuse_wait_idle();
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/* Program the target address and value */
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FUSE_REGS->FUSE_REG_ADDR = addr;
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FUSE_REGS->FUSE_REG_WRITE = value;
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/* Enable write operation in control register */
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uint32_t ctrl_val = FUSE_REGS->FUSE_CTRL;
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ctrl_val &= ~0x3;
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ctrl_val |= 0x2; /* Set FUSE_WRITE command */
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FUSE_REGS->FUSE_CTRL = ctrl_val;
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fuse_wait_idle();
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}
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/* Sense the fuse hardware array into the shadow cache */
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void fuse_hw_sense(void)
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{
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fuse_wait_idle();
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/* Enable sense operation in control register */
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uint32_t ctrl_val = FUSE_REGS->FUSE_CTRL;
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ctrl_val &= ~0x3;
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ctrl_val |= 0x3; /* Set FUSE_SENSE command */
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FUSE_REGS->FUSE_CTRL = ctrl_val;
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fuse_wait_idle();
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}
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/* Disables all fuse programming. */
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void fuse_disable_programming(void) {
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FUSE_REGS->FUSE_DIS_PGM = 1;
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}
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/* Unknown exactly what this does, but it alters the contents read from the fuse cache. */
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void fuse_secondary_private_key_disable(void) {
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FUSE_REGS->FUSE_PRIVATEKEYDISABLE = 0x10;
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}
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/* Read the SKU info register from the shadow cache */
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uint32_t fuse_get_sku_info(void)
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{
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return FUSE_CHIP_REGS->FUSE_SKU_INFO;
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}
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/* Read the bootrom patch version from a register in the shadow cache */
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uint32_t fuse_get_bootrom_patch_version(void)
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{
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return FUSE_CHIP_REGS->FUSE_SOC_SPEEDO_1;
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}
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/* Read a spare bit register from the shadow cache */
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uint32_t fuse_get_spare_bit(uint32_t idx)
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{
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if (idx >= 32) {
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return 0;
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}
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return FUSE_CHIP_REGS->FUSE_SPARE_BIT[idx];
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}
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/* Read a reserved ODM register from the shadow cache */
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uint32_t fuse_get_reserved_odm(uint32_t idx)
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{
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if (idx >= 8) {
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return 0;
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}
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return FUSE_CHIP_REGS->FUSE_RESERVED_ODM[idx];
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}
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uint32_t fuse_get_5x_key_generation(void) {
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if ((fuse_get_reserved_odm(4) & 0x800) && fuse_get_reserved_odm(0) == 0x8E61ECAE && fuse_get_reserved_odm(1) == 0xF2BA3BB2) {
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return fuse_get_reserved_odm(2) & 0x1F;
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} else {
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return 0;
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}
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}
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/* Derive the Device ID using values in the shadow cache */
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uint64_t fuse_get_device_id(void) {
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uint64_t device_id = 0;
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uint64_t y_coord = FUSE_CHIP_REGS->FUSE_Y_COORDINATE & 0x1FF;
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uint64_t x_coord = FUSE_CHIP_REGS->FUSE_X_COORDINATE & 0x1FF;
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uint64_t wafer_id = FUSE_CHIP_REGS->FUSE_WAFER_ID & 0x3F;
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uint32_t lot_code = FUSE_CHIP_REGS->FUSE_LOT_CODE_0;
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uint64_t fab_code = FUSE_CHIP_REGS->FUSE_FAB_CODE & 0x3F;
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uint64_t derived_lot_code = 0;
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for (unsigned int i = 0; i < 5; i++) {
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derived_lot_code = (derived_lot_code * 0x24) + ((lot_code >> (24 - 6*i)) & 0x3F);
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}
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derived_lot_code &= 0x03FFFFFF;
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device_id |= y_coord << 0;
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device_id |= x_coord << 9;
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device_id |= wafer_id << 18;
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device_id |= derived_lot_code << 24;
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device_id |= fab_code << 50;
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return device_id;
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}
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/* Get the DRAM ID using values in the shadow cache */
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uint32_t fuse_get_dram_id(void) {
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return (FUSE_CHIP_REGS->FUSE_RESERVED_ODM[4] >> 3) & 0x7;
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}
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/* Derive the Hardware Type using values in the shadow cache */
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uint32_t fuse_get_hardware_type(void) {
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/* This function is very different between 4.x and < 4.x */
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uint32_t hardware_type = ((FUSE_CHIP_REGS->FUSE_RESERVED_ODM[4] >> 7) & 2) | ((FUSE_CHIP_REGS->FUSE_RESERVED_ODM[4] >> 2) & 1);
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if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) {
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static const uint32_t types[] = {0,1,4,3};
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hardware_type |= (FUSE_CHIP_REGS->FUSE_RESERVED_ODM[4] >> 14) & 0x3C;
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hardware_type--;
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return hardware_type > 3 ? 4 : types[hardware_type];
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} else {
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if (hardware_type >= 1) {
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return hardware_type > 2 ? 3 : hardware_type - 1;
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} else if ((FUSE_CHIP_REGS->FUSE_SPARE_BIT[9] & 1) == 0) {
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return 0;
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} else {
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return 3;
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}
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}
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}
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/* Derive the Retail Type using values in the shadow cache */
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uint32_t fuse_get_retail_type(void) {
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/* Retail type = IS_RETAIL | UNIT_TYPE */
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uint32_t retail_type = ((FUSE_CHIP_REGS->FUSE_RESERVED_ODM[4] >> 7) & 4) | (FUSE_CHIP_REGS->FUSE_RESERVED_ODM[4] & 3);
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if (retail_type == 4) { /* Standard retail unit, IS_RETAIL | 0. */
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return 1;
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} else if (retail_type == 3) { /* Standard dev unit, 0 | DEV_UNIT. */
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return 0;
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}
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return 2; /* IS_RETAIL | DEV_UNIT */
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}
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/* Derive the 16-byte Hardware Info using values in the shadow cache, and copy to output buffer. */
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void fuse_get_hardware_info(void *dst) {
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uint32_t hw_info[0x4];
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uint32_t unk_hw_fuse = FUSE_CHIP_REGS->_0x120 & 0x3F;
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uint32_t y_coord = FUSE_CHIP_REGS->FUSE_Y_COORDINATE & 0x1FF;
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uint32_t x_coord = FUSE_CHIP_REGS->FUSE_X_COORDINATE & 0x1FF;
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uint32_t wafer_id = FUSE_CHIP_REGS->FUSE_WAFER_ID & 0x3F;
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uint32_t lot_code_0 = FUSE_CHIP_REGS->FUSE_LOT_CODE_0;
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uint32_t lot_code_1 = FUSE_CHIP_REGS->FUSE_LOT_CODE_1 & 0x0FFFFFFF;
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uint32_t fab_code = FUSE_CHIP_REGS->FUSE_FAB_CODE & 0x3F;
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uint32_t vendor_code = FUSE_CHIP_REGS->FUSE_VENDOR_CODE & 0xF;
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/* Hardware Info = unk_hw_fuse || Y_COORD || X_COORD || WAFER_ID || LOT_CODE || FAB_CODE || VENDOR_ID */
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hw_info[0] = (uint32_t)((lot_code_1 << 30) | (wafer_id << 24) | (x_coord << 15) | (y_coord << 6) | (unk_hw_fuse));
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hw_info[1] = (uint32_t)((lot_code_0 << 26) | (lot_code_1 >> 2));
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hw_info[2] = (uint32_t)((fab_code << 26) | (lot_code_0 >> 6));
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hw_info[3] = (uint32_t)(vendor_code);
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memcpy(dst, hw_info, 0x10);
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}
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