mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
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603 lines
29 KiB
C++
603 lines
29 KiB
C++
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <exosphere.hpp>
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#include "se_execute.hpp"
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namespace ams::se {
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namespace {
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constexpr inline int AesKeySizeMax = 256 / BITSIZEOF(u8);
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enum AesMode {
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AesMode_Aes128 = ((SE_CONFIG_ENC_MODE_AESMODE_KEY128 << SE_CONFIG_ENC_MODE_OFFSET) | (SE_CONFIG_DEC_MODE_AESMODE_KEY128 << SE_CONFIG_DEC_MODE_OFFSET)) >> SE_CONFIG_DEC_MODE_OFFSET,
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AesMode_Aes192 = ((SE_CONFIG_ENC_MODE_AESMODE_KEY192 << SE_CONFIG_ENC_MODE_OFFSET) | (SE_CONFIG_DEC_MODE_AESMODE_KEY192 << SE_CONFIG_DEC_MODE_OFFSET)) >> SE_CONFIG_DEC_MODE_OFFSET,
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AesMode_Aes256 = ((SE_CONFIG_ENC_MODE_AESMODE_KEY256 << SE_CONFIG_ENC_MODE_OFFSET) | (SE_CONFIG_DEC_MODE_AESMODE_KEY256 << SE_CONFIG_DEC_MODE_OFFSET)) >> SE_CONFIG_DEC_MODE_OFFSET,
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};
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enum MemoryInterface {
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MemoryInterface_Ahb = SE_CRYPTO_CONFIG_MEMIF_AHB,
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MemoryInterface_Mc = SE_CRYPTO_CONFIG_MEMIF_MCCIF,
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};
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constexpr inline u32 AesConfigEcb = reg::Encode(SE_REG_BITS_VALUE(CRYPTO_CONFIG_CTR_CNTN, 0),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_KEYSCH_BYPASS, DISABLE),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_IV_SELECT, ORIGINAL),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_VCTRAM_SEL, MEMORY),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_INPUT_SEL, MEMORY),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_XOR_POS, BYPASS),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_HASH_ENB, DISABLE));
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constexpr inline u32 AesConfigCtr = reg::Encode(SE_REG_BITS_VALUE(CRYPTO_CONFIG_CTR_CNTN, 1),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_KEYSCH_BYPASS, DISABLE),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_IV_SELECT, ORIGINAL),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_VCTRAM_SEL, MEMORY),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_INPUT_SEL, LINEAR_CTR),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_XOR_POS, BOTTOM),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_HASH_ENB, DISABLE));
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constexpr inline u32 AesConfigCmac = reg::Encode(SE_REG_BITS_VALUE(CRYPTO_CONFIG_CTR_CNTN, 0),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_KEYSCH_BYPASS, DISABLE),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_IV_SELECT, ORIGINAL),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_VCTRAM_SEL, INIT_AESOUT),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_INPUT_SEL, MEMORY),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_XOR_POS, TOP),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_HASH_ENB, ENABLE));
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constexpr inline u32 AesConfigCbcEncrypt = reg::Encode(SE_REG_BITS_VALUE(CRYPTO_CONFIG_CTR_CNTN, 0),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_KEYSCH_BYPASS, DISABLE),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_IV_SELECT, ORIGINAL),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_VCTRAM_SEL, INIT_AESOUT),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_INPUT_SEL, MEMORY),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_XOR_POS, TOP),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_HASH_ENB, DISABLE));
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constexpr inline u32 AesConfigCbcDecrypt = reg::Encode(SE_REG_BITS_VALUE(CRYPTO_CONFIG_CTR_CNTN, 0),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_KEYSCH_BYPASS, DISABLE),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_IV_SELECT, ORIGINAL),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_VCTRAM_SEL, INIT_PREV_MEMORY),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_INPUT_SEL, MEMORY),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_XOR_POS, BOTTOM),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_HASH_ENB, DISABLE));
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void SetConfig(volatile SecurityEngineRegisters *SE, bool encrypt, SE_CONFIG_DST dst) {
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reg::Write(SE->SE_CONFIG, SE_REG_BITS_ENUM (CONFIG_ENC_MODE, AESMODE_KEY128),
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SE_REG_BITS_ENUM (CONFIG_DEC_MODE, AESMODE_KEY128),
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SE_REG_BITS_ENUM_SEL(CONFIG_ENC_ALG, encrypt, AES_ENC, NOP),
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SE_REG_BITS_ENUM_SEL(CONFIG_DEC_ALG, encrypt, NOP, AES_DEC),
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SE_REG_BITS_VALUE (CONFIG_DST, dst));
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}
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void SetAesConfig(volatile SecurityEngineRegisters *SE, int slot, bool encrypt, u32 config) {
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const u32 encoded = reg::Encode(SE_REG_BITS_ENUM (CRYPTO_CONFIG_MEMIF, AHB),
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SE_REG_BITS_VALUE (CRYPTO_CONFIG_KEY_INDEX, slot),
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SE_REG_BITS_ENUM_SEL(CRYPTO_CONFIG_CORE_SEL, encrypt, ENCRYPT, DECRYPT));
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reg::Write(SE->SE_CRYPTO_CONFIG, (config | encoded));
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}
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void SetBlockCount(volatile SecurityEngineRegisters *SE, int count) {
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reg::Write(SE->SE_CRYPTO_LAST_BLOCK, count - 1);
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}
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void UpdateAesMode(volatile SecurityEngineRegisters *SE, AesMode mode) {
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reg::ReadWrite(SE->SE_CONFIG, REG_BITS_VALUE(16, 16, mode));
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}
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void UpdateMemoryInterface(volatile SecurityEngineRegisters *SE, MemoryInterface memif) {
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reg::ReadWrite(SE->SE_CRYPTO_CONFIG, SE_REG_BITS_VALUE(CRYPTO_CONFIG_MEMIF, memif));
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}
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void SetCounter(volatile SecurityEngineRegisters *SE, const void *ctr) {
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const u32 *ctr_32 = reinterpret_cast<const u32 *>(ctr);
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/* Copy the input ctr to the linear CTR registers. */
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reg::Write(SE->SE_CRYPTO_LINEAR_CTR[0], util::LoadLittleEndian(ctr_32 + 0));
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reg::Write(SE->SE_CRYPTO_LINEAR_CTR[1], util::LoadLittleEndian(ctr_32 + 1));
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reg::Write(SE->SE_CRYPTO_LINEAR_CTR[2], util::LoadLittleEndian(ctr_32 + 2));
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reg::Write(SE->SE_CRYPTO_LINEAR_CTR[3], util::LoadLittleEndian(ctr_32 + 3));
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}
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void SetAesKeyIv(volatile SecurityEngineRegisters *SE, int slot, const void *iv, size_t iv_size) {
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AMS_ABORT_UNLESS(0 <= slot && slot < AesKeySlotCount);
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AMS_ABORT_UNLESS(iv_size <= AesBlockSize);
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/* Set each iv word in order. */
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const u32 *iv_u32 = static_cast<const u32 *>(iv);
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const int num_words = iv_size / sizeof(u32);
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for (int i = 0; i < num_words; ++i) {
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/* Select the keyslot. */
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reg::Write(SE->SE_CRYPTO_KEYTABLE_ADDR, SE_REG_BITS_VALUE(CRYPTO_KEYTABLE_ADDR_KEYIV_KEY_SLOT, slot),
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SE_REG_BITS_ENUM (CRYPTO_KEYTABLE_ADDR_KEYIV_KEYIV_SEL, IV),
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SE_REG_BITS_ENUM (CRYPTO_KEYTABLE_ADDR_KEYIV_IV_SEL, ORIGINAL_IV),
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SE_REG_BITS_VALUE(CRYPTO_KEYTABLE_ADDR_KEYIV_KEY_WORD, i));
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/* Set the iv word. */
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SE->SE_CRYPTO_KEYTABLE_DATA = *(iv_u32++);
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}
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}
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void SetEncryptedAesKey(int dst_slot, int kek_slot, const void *key, size_t key_size, AesMode mode) {
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AMS_ABORT_UNLESS(key_size <= AesKeySizeMax);
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AMS_ABORT_UNLESS(0 <= dst_slot && dst_slot < AesKeySlotCount);
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AMS_ABORT_UNLESS(0 <= kek_slot && kek_slot < AesKeySlotCount);
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/* Get the engine. */
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auto *SE = GetRegisters();
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/* Configure for single AES ECB decryption to key table. */
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SetConfig(SE, false, SE_CONFIG_DST_KEYTABLE);
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SetAesConfig(SE, kek_slot, false, AesConfigEcb);
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UpdateAesMode(SE, mode);
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SetBlockCount(SE, 1);
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/* Select the destination keyslot. */
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reg::Write(SE->SE_CRYPTO_KEYTABLE_DST, SE_REG_BITS_VALUE(CRYPTO_KEYTABLE_DST_KEY_INDEX, dst_slot), SE_REG_BITS_ENUM(CRYPTO_KEYTABLE_DST_WORD_QUAD, KEYS_0_3));
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/* Ensure that the se sees the keydata we want it to. */
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hw::FlushDataCache(key, key_size);
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hw::DataSynchronizationBarrierInnerShareable();
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/* Execute the operation. */
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ExecuteOperation(SE, SE_OPERATION_OP_START, nullptr, 0, key, key_size);
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}
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void EncryptAes(void *dst, size_t dst_size, int slot, const void *src, size_t src_size, AesMode mode) {
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/* If nothing to decrypt, succeed. */
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if (src_size == 0) { return; }
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/* Validate input. */
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AMS_ABORT_UNLESS(dst_size == AesBlockSize);
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AMS_ABORT_UNLESS(src_size == AesBlockSize);
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AMS_ABORT_UNLESS(0 <= slot && slot < AesKeySlotCount);
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/* Get the engine. */
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auto *SE = GetRegisters();
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/* Configure for AES-ECB encryption to memory. */
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SetConfig(SE, true, SE_CONFIG_DST_MEMORY);
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SetAesConfig(SE, slot, true, AesConfigEcb);
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UpdateAesMode(SE, mode);
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/* Execute the operation. */
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ExecuteOperationSingleBlock(SE, dst, dst_size, src, src_size);
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}
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void ExpandSubkey(u8 *subkey) {
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/* Shift everything left one bit. */
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u8 prev = 0;
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for (int i = AesBlockSize - 1; i >= 0; --i) {
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const u8 top = (subkey[i] >> 7);
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subkey[i] = ((subkey[i] << 1) | prev);
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prev = top;
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}
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/* And xor with Rb if necessary. */
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if (prev != 0) {
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subkey[AesBlockSize - 1] ^= 0x87;
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}
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}
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void GetCmacResult(volatile SecurityEngineRegisters *SE, void *dst, size_t dst_size) {
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const int num_words = dst_size / sizeof(u32);
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for (int i = 0; i < num_words; ++i) {
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reg::Write(static_cast<u32 *>(dst) + i, reg::Read(SE->SE_HASH_RESULT[i]));
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}
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}
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void ComputeAesCmac(void *dst, size_t dst_size, int slot, const void *src, size_t src_size, AesMode mode) {
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/* Validate input. */
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AMS_ABORT_UNLESS(0 <= slot && slot < AesKeySlotCount);
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/* Get the engine. */
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auto *SE = GetRegisters();
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/* Determine mac extents. */
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const int num_blocks = util::DivideUp(src_size, AesBlockSize);
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const size_t last_block_size = (src_size == 0) ? 0 : (src_size - ((num_blocks - 1) * AesBlockSize));
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/* Create subkey. */
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u8 subkey[AesBlockSize];
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{
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/* Encrypt zeroes. */
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std::memset(subkey, 0, sizeof(subkey));
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EncryptAes(subkey, sizeof(subkey), slot, subkey, sizeof(subkey), mode);
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/* Expand. */
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ExpandSubkey(subkey);
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/* Account for last block. */
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if (last_block_size != AesBlockSize) {
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ExpandSubkey(subkey);
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}
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}
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/* Configure for AES-CMAC. */
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SetConfig(SE, true, SE_CONFIG_DST_HASH_REG);
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SetAesConfig(SE, slot, true, AesConfigCmac);
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UpdateAesMode(SE, mode);
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/* Set the IV to zero. */
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for (int i = 0; i < 4; ++i) {
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/* Select the keyslot. */
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reg::Write(SE->SE_CRYPTO_KEYTABLE_ADDR, SE_REG_BITS_VALUE(CRYPTO_KEYTABLE_ADDR_KEYIV_KEY_SLOT, slot),
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SE_REG_BITS_ENUM (CRYPTO_KEYTABLE_ADDR_KEYIV_KEYIV_SEL, IV),
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SE_REG_BITS_ENUM (CRYPTO_KEYTABLE_ADDR_KEYIV_IV_SEL, ORIGINAL_IV),
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SE_REG_BITS_VALUE(CRYPTO_KEYTABLE_ADDR_KEYIV_KEY_WORD, i));
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/* Set the iv word. */
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SE->SE_CRYPTO_KEYTABLE_DATA = 0;
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}
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/* Handle blocks before the last. */
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if (num_blocks > 1) {
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SetBlockCount(SE, num_blocks - 1);
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ExecuteOperation(SE, SE_OPERATION_OP_START, nullptr, 0, src, src_size);
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reg::ReadWrite(SE->SE_CRYPTO_CONFIG, SE_REG_BITS_ENUM(CRYPTO_CONFIG_IV_SELECT, UPDATED));
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}
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/* Handle the last block. */
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{
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SetBlockCount(SE, 1);
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/* Create the last block. */
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u8 last_block[AesBlockSize];
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if (last_block_size < sizeof(last_block)) {
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std::memset(last_block, 0, sizeof(last_block));
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last_block[last_block_size] = 0x80;
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}
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std::memcpy(last_block, static_cast<const u8 *>(src) + src_size - last_block_size, last_block_size);
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/* Xor with the subkey. */
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for (size_t i = 0; i < AesBlockSize; ++i) {
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last_block[i] ^= subkey[i];
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}
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/* Ensure the SE sees correct data. */
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hw::FlushDataCache(last_block, sizeof(last_block));
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hw::DataSynchronizationBarrierInnerShareable();
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ExecuteOperation(SE, SE_OPERATION_OP_START, nullptr, 0, last_block, sizeof(last_block));
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}
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/* Get the output. */
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GetCmacResult(SE, dst, dst_size);
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}
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void EncryptAesCbc(void *dst, size_t dst_size, int slot, const void *src, size_t src_size, const void *iv, size_t iv_size, AesMode mode) {
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/* If nothing to encrypt, succeed. */
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if (src_size == 0) { return; }
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/* Validate input. */
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AMS_ABORT_UNLESS(iv_size == AesBlockSize);
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AMS_ABORT_UNLESS(0 <= slot && slot < AesKeySlotCount);
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/* Get the engine. */
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auto *SE = GetRegisters();
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/* Determine extents. */
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const size_t num_blocks = src_size / AesBlockSize;
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const size_t aligned_size = num_blocks * AesBlockSize;
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AMS_ABORT_UNLESS(src_size == aligned_size);
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/* Configure for aes-cbc encryption. */
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SetConfig(SE, true, SE_CONFIG_DST_MEMORY);
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SetAesConfig(SE, slot, true, AesConfigCbcEncrypt);
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UpdateAesMode(SE, mode);
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/* Set the iv. */
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SetAesKeyIv(SE, slot, iv, iv_size);
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/* Set the block count. */
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SetBlockCount(SE, num_blocks);
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/* Execute the operation. */
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ExecuteOperation(SE, SE_OPERATION_OP_START, dst, dst_size, src, aligned_size);
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}
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void DecryptAesCbc(void *dst, size_t dst_size, int slot, const void *src, size_t src_size, const void *iv, size_t iv_size, AesMode mode) {
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/* If nothing to decrypt, succeed. */
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if (src_size == 0) { return; }
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/* Validate input. */
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AMS_ABORT_UNLESS(iv_size == AesBlockSize);
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AMS_ABORT_UNLESS(0 <= slot && slot < AesKeySlotCount);
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/* Get the engine. */
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auto *SE = GetRegisters();
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/* Determine extents. */
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const size_t num_blocks = src_size / AesBlockSize;
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const size_t aligned_size = num_blocks * AesBlockSize;
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AMS_ABORT_UNLESS(src_size == aligned_size);
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/* Configure for aes-cbc encryption. */
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SetConfig(SE, false, SE_CONFIG_DST_MEMORY);
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SetAesConfig(SE, slot, false, AesConfigCbcDecrypt);
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UpdateAesMode(SE, mode);
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/* Set the iv. */
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SetAesKeyIv(SE, slot, iv, iv_size);
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/* Set the block count. */
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SetBlockCount(SE, num_blocks);
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/* Execute the operation. */
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ExecuteOperation(SE, SE_OPERATION_OP_START, dst, dst_size, src, aligned_size);
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}
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void ComputeAes128Async(u32 out_ll_address, int slot, u32 in_ll_address, u32 size, DoneHandler handler, u32 config, bool encrypt, volatile SecurityEngineRegisters *SE) {
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/* If nothing to decrypt, succeed. */
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if (size == 0) { return; }
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/* Validate input. */
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AMS_ABORT_UNLESS(0 <= slot && slot < AesKeySlotCount);
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/* Configure for the specific operation. */
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SetConfig(SE, encrypt, SE_CONFIG_DST_MEMORY);
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SetAesConfig(SE, slot, encrypt, config);
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UpdateMemoryInterface(SE, MemoryInterface_Mc);
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/* Configure the number of blocks. */
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const int num_blocks = size / AesBlockSize;
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SetBlockCount(SE, num_blocks);
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/* Set the done handler. */
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SetDoneHandler(SE, handler);
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/* Start the raw operation. */
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StartOperationRaw(SE, SE_OPERATION_OP_START, out_ll_address, in_ll_address);
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}
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}
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void ClearAesKeySlot(int slot) {
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/* Validate the key slot. */
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AMS_ABORT_UNLESS(0 <= slot && slot < AesKeySlotCount);
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/* Get the engine. */
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auto *SE = GetRegisters();
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for (int i = 0; i < 16; ++i) {
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/* Select the keyslot. */
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reg::Write(SE->SE_CRYPTO_KEYTABLE_ADDR, SE_REG_BITS_VALUE(CRYPTO_KEYTABLE_ADDR_KEYIV_KEY_SLOT, slot), SE_REG_BITS_VALUE(CRYPTO_KEYTABLE_ADDR_KEYIV_WORD, i));
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/* Write the data. */
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SE->SE_CRYPTO_KEYTABLE_DATA = 0;
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}
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}
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void ClearAesKeyIv(int slot) {
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/* Validate the key slot. */
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AMS_ABORT_UNLESS(0 <= slot && slot < AesKeySlotCount);
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/* Get the engine. */
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auto *SE = GetRegisters();
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/* Set each iv word in order. */
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for (int i = 0; i < 4; ++i) {
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/* Select the keyslot original iv. */
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reg::Write(SE->SE_CRYPTO_KEYTABLE_ADDR, SE_REG_BITS_VALUE(CRYPTO_KEYTABLE_ADDR_KEYIV_KEY_SLOT, slot),
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SE_REG_BITS_ENUM (CRYPTO_KEYTABLE_ADDR_KEYIV_KEYIV_SEL, IV),
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SE_REG_BITS_ENUM (CRYPTO_KEYTABLE_ADDR_KEYIV_IV_SEL, ORIGINAL_IV),
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SE_REG_BITS_VALUE(CRYPTO_KEYTABLE_ADDR_KEYIV_KEY_WORD, i));
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/* Set the iv word. */
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SE->SE_CRYPTO_KEYTABLE_DATA = 0;
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/* Select the keyslot updated iv. */
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reg::Write(SE->SE_CRYPTO_KEYTABLE_ADDR, SE_REG_BITS_VALUE(CRYPTO_KEYTABLE_ADDR_KEYIV_KEY_SLOT, slot),
|
|
SE_REG_BITS_ENUM (CRYPTO_KEYTABLE_ADDR_KEYIV_KEYIV_SEL, IV),
|
|
SE_REG_BITS_ENUM (CRYPTO_KEYTABLE_ADDR_KEYIV_IV_SEL, UPDATED_IV),
|
|
SE_REG_BITS_VALUE(CRYPTO_KEYTABLE_ADDR_KEYIV_KEY_WORD, i));
|
|
|
|
/* Set the iv word. */
|
|
SE->SE_CRYPTO_KEYTABLE_DATA = 0;
|
|
}
|
|
}
|
|
|
|
void LockAesKeySlot(int slot, u32 flags) {
|
|
/* Validate the key slot. */
|
|
AMS_ABORT_UNLESS(0 <= slot && slot < AesKeySlotCount);
|
|
|
|
/* Get the engine. */
|
|
auto *SE = GetRegisters();
|
|
|
|
/* Set non per-key flags. */
|
|
if ((flags & ~KeySlotLockFlags_PerKey) != 0) {
|
|
/* KeySlotLockFlags_DstKeyTableOnly is Mariko-only. */
|
|
if (fuse::GetSocType() == fuse::SocType_Mariko) {
|
|
reg::ReadWrite(SE->SE_CRYPTO_KEYTABLE_ACCESS[slot], REG_BITS_VALUE(0, 7, ~flags), REG_BITS_VALUE(7, 1, ((flags & KeySlotLockFlags_DstKeyTableOnly) != 0) ? 1 : 0));
|
|
} else {
|
|
reg::ReadWrite(SE->SE_CRYPTO_KEYTABLE_ACCESS[slot], REG_BITS_VALUE(0, 7, ~flags));
|
|
}
|
|
}
|
|
|
|
/* Set per-key flag. */
|
|
if ((flags & KeySlotLockFlags_PerKey) != 0) {
|
|
reg::ReadWrite(SE->SE_CRYPTO_SECURITY_PERKEY, REG_BITS_VALUE(slot, 1, 0));
|
|
}
|
|
}
|
|
|
|
void SetAesKey(int slot, const void *key, size_t key_size) {
|
|
/* Validate the key slot and key size. */
|
|
AMS_ABORT_UNLESS(0 <= slot && slot < AesKeySlotCount);
|
|
AMS_ABORT_UNLESS(key_size <= AesKeySizeMax);
|
|
|
|
/* Get the engine. */
|
|
auto *SE = GetRegisters();
|
|
|
|
/* Set each key word in order. */
|
|
const u32 *key_u32 = static_cast<const u32 *>(key);
|
|
const int num_words = key_size / sizeof(u32);
|
|
for (int i = 0; i < num_words; ++i) {
|
|
/* Select the keyslot. */
|
|
reg::Write(SE->SE_CRYPTO_KEYTABLE_ADDR, SE_REG_BITS_VALUE(CRYPTO_KEYTABLE_ADDR_KEYIV_KEY_SLOT, slot),
|
|
SE_REG_BITS_ENUM (CRYPTO_KEYTABLE_ADDR_KEYIV_KEYIV_SEL, KEY),
|
|
SE_REG_BITS_VALUE(CRYPTO_KEYTABLE_ADDR_KEYIV_KEY_WORD, i));
|
|
|
|
/* Set the key word. */
|
|
SE->SE_CRYPTO_KEYTABLE_DATA = *(key_u32++);
|
|
}
|
|
}
|
|
|
|
void SetEncryptedAesKey128(int dst_slot, int kek_slot, const void *key, size_t key_size) {
|
|
return SetEncryptedAesKey(dst_slot, kek_slot, key, key_size, AesMode_Aes128);
|
|
}
|
|
|
|
void SetEncryptedAesKey256(int dst_slot, int kek_slot, const void *key, size_t key_size) {
|
|
return SetEncryptedAesKey(dst_slot, kek_slot, key, key_size, AesMode_Aes256);
|
|
}
|
|
|
|
void EncryptAes128(void *dst, size_t dst_size, int slot, const void *src, size_t src_size) {
|
|
return EncryptAes(dst, dst_size, slot, src, src_size, AesMode_Aes128);
|
|
}
|
|
|
|
void DecryptAes128(void *dst, size_t dst_size, int slot, const void *src, size_t src_size) {
|
|
/* If nothing to decrypt, succeed. */
|
|
if (src_size == 0) { return; }
|
|
|
|
/* Validate input. */
|
|
AMS_ABORT_UNLESS(dst_size == AesBlockSize);
|
|
AMS_ABORT_UNLESS(src_size == AesBlockSize);
|
|
AMS_ABORT_UNLESS(0 <= slot && slot < AesKeySlotCount);
|
|
|
|
/* Get the engine. */
|
|
auto *SE = GetRegisters();
|
|
|
|
/* Configure for AES-ECB decryption to memory. */
|
|
SetConfig(SE, false, SE_CONFIG_DST_MEMORY);
|
|
SetAesConfig(SE, slot, false, AesConfigEcb);
|
|
|
|
ExecuteOperationSingleBlock(SE, dst, dst_size, src, src_size);
|
|
}
|
|
|
|
void ComputeAes128Ctr(void *dst, size_t dst_size, int slot, const void *src, size_t src_size, const void *iv, size_t iv_size) {
|
|
/* If nothing to do, succeed. */
|
|
if (src_size == 0) { return; }
|
|
|
|
/* Validate input. */
|
|
AMS_ABORT_UNLESS(iv_size == AesBlockSize);
|
|
AMS_ABORT_UNLESS(0 <= slot && slot < AesKeySlotCount);
|
|
|
|
/* Get the engine. */
|
|
auto *SE = GetRegisters();
|
|
|
|
/* Determine how many full blocks we can operate on. */
|
|
const size_t num_blocks = src_size / AesBlockSize;
|
|
const size_t aligned_size = num_blocks * AesBlockSize;
|
|
const size_t fractional = src_size - aligned_size;
|
|
|
|
/* Here Nintendo writes 1 to SE_SPARE. It's unclear why they do this, but we will do so as well. */
|
|
SE->SE_SPARE = 0x1;
|
|
|
|
/* Configure for AES-CTR encryption/decryption to memory. */
|
|
SetConfig(SE, true, SE_CONFIG_DST_MEMORY);
|
|
SetAesConfig(SE, slot, true, AesConfigCtr);
|
|
|
|
/* Set the counter. */
|
|
SetCounter(SE, iv);
|
|
|
|
/* Process as many aligned blocks as we can. */
|
|
if (aligned_size > 0) {
|
|
/* Configure the engine to process the right number of blocks. */
|
|
SetBlockCount(SE, num_blocks);
|
|
|
|
/* Execute the operation. */
|
|
ExecuteOperation(SE, SE_OPERATION_OP_START, dst, dst_size, src, aligned_size);
|
|
|
|
/* Synchronize around this point. */
|
|
hw::DataSynchronizationBarrierInnerShareable();
|
|
}
|
|
|
|
/* Process a single block to output. */
|
|
if (fractional > 0 && dst_size > aligned_size) {
|
|
const size_t copy_size = std::min(fractional, dst_size - aligned_size);
|
|
|
|
ExecuteOperationSingleBlock(SE, static_cast<u8 *>(dst) + aligned_size, copy_size, static_cast<const u8 *>(src) + aligned_size, fractional);
|
|
}
|
|
}
|
|
|
|
void ComputeAes128Cmac(void *dst, size_t dst_size, int slot, const void *src, size_t src_size) {
|
|
return ComputeAesCmac(dst, dst_size, slot, src, src_size, AesMode_Aes128);
|
|
}
|
|
|
|
void ComputeAes256Cmac(void *dst, size_t dst_size, int slot, const void *src, size_t src_size) {
|
|
return ComputeAesCmac(dst, dst_size, slot, src, src_size, AesMode_Aes256);
|
|
}
|
|
|
|
void EncryptAes128Cbc(void *dst, size_t dst_size, int slot, const void *src, size_t src_size, const void *iv, size_t iv_size) {
|
|
return EncryptAesCbc(dst, dst_size, slot, src, src_size, iv, iv_size, AesMode_Aes128);
|
|
}
|
|
|
|
void EncryptAes256Cbc(void *dst, size_t dst_size, int slot, const void *src, size_t src_size, const void *iv, size_t iv_size) {
|
|
return EncryptAesCbc(dst, dst_size, slot, src, src_size, iv, iv_size, AesMode_Aes256);
|
|
}
|
|
|
|
void DecryptAes128Cbc(void *dst, size_t dst_size, int slot, const void *src, size_t src_size, const void *iv, size_t iv_size) {
|
|
return DecryptAesCbc(dst, dst_size, slot, src, src_size, iv, iv_size, AesMode_Aes128);
|
|
}
|
|
|
|
void DecryptAes256Cbc(void *dst, size_t dst_size, int slot, const void *src, size_t src_size, const void *iv, size_t iv_size) {
|
|
return DecryptAesCbc(dst, dst_size, slot, src, src_size, iv, iv_size, AesMode_Aes256);
|
|
}
|
|
|
|
void EncryptAes128CbcAsync(u32 out_ll_address, int slot, u32 in_ll_address, u32 size, const void *iv, size_t iv_size, DoneHandler handler) {
|
|
/* Validate the iv. */
|
|
AMS_ABORT_UNLESS(iv_size == AesBlockSize);
|
|
|
|
/* Get the registers. */
|
|
volatile auto *SE = GetRegisters();
|
|
|
|
/* Set the iv. */
|
|
SetAesKeyIv(SE, slot, iv, iv_size);
|
|
|
|
/* Perform the asynchronous aes operation. */
|
|
ComputeAes128Async(out_ll_address, slot, in_ll_address, size, handler, AesConfigCbcEncrypt, true, SE);
|
|
}
|
|
|
|
void DecryptAes128CbcAsync(u32 out_ll_address, int slot, u32 in_ll_address, u32 size, const void *iv, size_t iv_size, DoneHandler handler) {
|
|
/* Validate the iv. */
|
|
AMS_ABORT_UNLESS(iv_size == AesBlockSize);
|
|
|
|
/* Get the registers. */
|
|
volatile auto *SE = GetRegisters();
|
|
|
|
/* Set the iv. */
|
|
SetAesKeyIv(SE, slot, iv, iv_size);
|
|
|
|
/* Perform the asynchronous aes operation. */
|
|
ComputeAes128Async(out_ll_address, slot, in_ll_address, size, handler, AesConfigCbcDecrypt, false, SE);
|
|
}
|
|
|
|
void ComputeAes128CtrAsync(u32 out_ll_address, int slot, u32 in_ll_address, u32 size, const void *iv, size_t iv_size, DoneHandler handler) {
|
|
/* Validate the iv. */
|
|
AMS_ABORT_UNLESS(iv_size == AesBlockSize);
|
|
|
|
/* Get the registers. */
|
|
volatile auto *SE = GetRegisters();
|
|
|
|
/* Here Nintendo writes 1 to SE_SPARE. It's unclear why they do this, but we will do so as well. */
|
|
SE->SE_SPARE = 0x1;
|
|
|
|
/* Set the counter. */
|
|
SetCounter(SE, iv);
|
|
|
|
/* Perform the asynchronous aes operation. */
|
|
ComputeAes128Async(out_ll_address, slot, in_ll_address, size, handler, AesConfigCtr, true, SE);
|
|
}
|
|
|
|
}
|