mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
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224 lines
6.2 KiB
C
224 lines
6.2 KiB
C
/*
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* Copyright (c) 2018-2019 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdint.h>
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#include "utils.h"
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#include "car.h"
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#include "timers.h"
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#include "di.h"
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#include "se.h"
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#include "fuse.h"
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#include "pmc.h"
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#include "mc.h"
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#include "sysreg.h"
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#include "tsec.h"
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#define I2S_BASE 0x702D1000
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#define MAKE_I2S_REG(n) MAKE_REG32(I2S_BASE + n)
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static void setup_exception_vectors(void) {
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for (unsigned int i = 0; i < 0x20; i += 4) {
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MAKE_REG32(0x6000F200u + i) = (uint32_t)generic_panic;
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}
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}
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static void mbist_workaround(void)
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{
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volatile tegra_car_t *car = car_get_regs();
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car->clk_source_sor1 = ((car->clk_source_sor1 | 0x8000) & 0xFFFFBFFF);
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car->plld_base |= 0x40800000u;
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car->rst_dev_y_clr = 0x40;
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car->rst_dev_x_clr = 0x40000;
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car->rst_dev_l_clr = 0x18000000;
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udelay(3);
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/* Setup I2S. */
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MAKE_I2S_REG(0x0A0) |= 0x400;
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MAKE_I2S_REG(0x088) &= 0xFFFFFFFE;
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MAKE_I2S_REG(0x1A0) |= 0x400;
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MAKE_I2S_REG(0x188) &= 0xFFFFFFFE;
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MAKE_I2S_REG(0x2A0) |= 0x400;
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MAKE_I2S_REG(0x288) &= 0xFFFFFFFE;
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MAKE_I2S_REG(0x3A0) |= 0x400;
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MAKE_I2S_REG(0x388) &= 0xFFFFFFFE;
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MAKE_I2S_REG(0x4A0) |= 0x400;
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MAKE_I2S_REG(0x488) &= 0xFFFFFFFE;
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MAKE_DI_REG(DC_COM_DSC_TOP_CTL) |= 4;
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MAKE_VIC_REG(0x8C) = 0xFFFFFFFF;
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udelay(3);
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/* Set devices in reset. */
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car->rst_dev_y_set = 0x40;
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car->rst_dev_l_set = 0x18000000;
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car->rst_dev_x_set = 0x40000;
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/* Clock out enables. */
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car->clk_out_enb_h = 0xC0;
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car->clk_out_enb_l = 0x80000130;
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car->clk_out_enb_u = 0x1F00200;
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car->clk_out_enb_v = 0x80400808;
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car->clk_out_enb_w = 0x402000FC;
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car->clk_out_enb_x = 0x23000780;
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car->clk_out_enb_y = 0x300;
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/* LVL2 clock gate overrides. */
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car->lvl2_clk_gate_ovra = 0;
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car->lvl2_clk_gate_ovrb = 0;
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car->lvl2_clk_gate_ovrc = 0;
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car->lvl2_clk_gate_ovrd = 0;
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car->lvl2_clk_gate_ovre = 0;
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/* Configure clock sources. */
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car->plld_base &= 0x1F7FFFFF;
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car->clk_source_sor1 &= 0xFFFF3FFF;
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car->clk_source_vi = ((car->clk_source_vi & 0x1FFFFFFF) | 0x80000000);
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car->clk_source_host1x = ((car->clk_source_host1x & 0x1FFFFFFF) | 0x80000000);
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car->clk_source_nvenc = ((car->clk_source_nvenc & 0x1FFFFFFF) | 0x80000000);
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}
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static int tsec_dma_wait_idle()
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{
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volatile tegra_tsec_t *tsec = tsec_get_regs();
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uint32_t timeout = (get_time_us() + 10000000);
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while (!(tsec->FALCON_DMATRFCMD & 2))
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if (get_time_us() > timeout)
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return 0;
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return 1;
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}
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static int tsec_dma_phys_to_flcn(bool is_imem, uint32_t flcn_offset, uint32_t phys_offset)
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{
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volatile tegra_tsec_t *tsec = tsec_get_regs();
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uint32_t cmd = 0;
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if (!is_imem)
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cmd = 0x600;
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else
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cmd = 0x10;
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tsec->FALCON_DMATRFMOFFS = flcn_offset;
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tsec->FALCON_DMATRFFBOFFS = phys_offset;
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tsec->FALCON_DMATRFCMD = cmd;
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return tsec_dma_wait_idle();
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}
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int load_tsec_fw(void) {
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volatile uint32_t* tsec_fw = (volatile uint32_t*)0x40010F00;
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const uint32_t tsec_fw_length = MAKE_REG32(0x40010EFC);
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volatile tegra_tsec_t *tsec = tsec_get_regs();
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/* Enable clocks. */
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clkrst_reboot(CARDEVICE_HOST1X);
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clkrst_reboot(CARDEVICE_TSEC);
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clkrst_reboot(CARDEVICE_SOR_SAFE);
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clkrst_reboot(CARDEVICE_SOR0);
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clkrst_reboot(CARDEVICE_SOR1);
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clkrst_reboot(CARDEVICE_KFUSE);
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/* Configure Falcon. */
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tsec->FALCON_DMACTL = 0;
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tsec->FALCON_IRQMSET = 0xFFF2;
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tsec->FALCON_IRQDEST = 0xFFF0;
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tsec->FALCON_ITFEN = 3;
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if (!tsec_dma_wait_idle())
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{
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/* Disable clocks. */
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clkrst_disable(CARDEVICE_KFUSE);
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clkrst_disable(CARDEVICE_SOR1);
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clkrst_disable(CARDEVICE_SOR0);
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clkrst_disable(CARDEVICE_SOR_SAFE);
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clkrst_disable(CARDEVICE_TSEC);
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clkrst_disable(CARDEVICE_HOST1X);
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return -1;
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}
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/* Load firmware. */
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tsec->FALCON_DMATRFBASE = (uint32_t)tsec_fw >> 8;
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for (uint32_t addr = 0; addr < tsec_fw_length; addr += 0x100)
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{
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if (!tsec_dma_phys_to_flcn(true, addr, addr))
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{
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/* Disable clocks. */
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clkrst_disable(CARDEVICE_KFUSE);
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clkrst_disable(CARDEVICE_SOR1);
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clkrst_disable(CARDEVICE_SOR0);
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clkrst_disable(CARDEVICE_SOR_SAFE);
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clkrst_disable(CARDEVICE_TSEC);
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clkrst_disable(CARDEVICE_HOST1X);
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return -2;
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}
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}
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/* Unknown host1x write. */
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MAKE_HOST1X_REG(0x3300) = 0x34C2E1DA;
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/* Execute firmware. */
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tsec->FALCON_SCRATCH1 = 0;
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tsec->FALCON_SCRATCH0 = 1;
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tsec->FALCON_BOOTVEC = 0;
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tsec->FALCON_CPUCTL = 2;
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while (true) {
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/* Yield to Nintendo's TSEC firmware. */
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}
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}
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int main(void) {
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/* Setup vectors */
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setup_exception_vectors();
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volatile tegra_pmc_t *pmc = pmc_get_regs();
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volatile tegra_car_t *car = car_get_regs();
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/* Clear the boot reason to avoid problems later */
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pmc->scratch200 = 0;
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pmc->reset_status = 0;
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//AHB_AHB_SPARE_REG_0 &= 0xFFFFFF9F;
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//pmc->scratch49 = (((pmc->scratch49 >> 1) << 1) & 0xFFFFFFFD);
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/* Apply the memory built-in self test workaround. */
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mbist_workaround();
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/* Reboot SE. */
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clkrst_reboot(CARDEVICE_SE);
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/* Initialize the fuse driver. */
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fuse_init();
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/* Don't bother checking SKU, fuses, or bootloader version. */
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mc_enable_for_tsec();
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/* 7.0.0 package1ldr holds I2C5 in reset, clears SYS clock. */
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car->clk_source_sys = 0;
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rst_enable(CARDEVICE_I2C5);
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load_tsec_fw();
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while (true) { }
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return 0;
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}
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