mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
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178 lines
6.6 KiB
C
178 lines
6.6 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef EXOSPHERE_UART_H
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#define EXOSPHERE_UART_H
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#include <stdint.h>
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#include "memory_map.h"
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/* Exosphere driver for the Tegra X1 UARTs. */
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static inline uintptr_t get_uart_base(void) {
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return MMIO_GET_DEVICE_ADDRESS(MMIO_DEVID_UART);
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}
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#define UART_BASE (get_uart_base())
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#define BAUD_115200 115200
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/* Exosphère: add the clkreset values for UART C,D,E */
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typedef enum {
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UART_A = 0,
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UART_B = 1,
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UART_C = 2,
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UART_D = 3,
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UART_E = 4,
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} UartDevice;
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/* 36.3.12 UART_VENDOR_STATUS_0_0 */
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typedef enum {
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UART_VENDOR_STATE_TX_IDLE = 1 << 0,
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UART_VENDOR_STATE_RX_IDLE = 1 << 1,
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/* This bit is set to 1 when a read is issued to an empty FIFO and gets cleared on register read (sticky bit until read)
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0 = NO_UNDERRUN
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1 = UNDERRUN
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*/
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UART_VENDOR_STATE_RX_UNDERRUN = 1 << 2,
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/* This bit is set to 1 when write data is issued to the TX FIFO when it is already full and gets cleared on register read (sticky bit until read)
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0 = NO_OVERRUN
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1 = OVERRUN
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*/
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UART_VENDOR_STATE_TX_OVERRUN = 1 << 3,
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UART_VENDOR_STATE_RX_FIFO_COUNTER = 0b111111 << 16, /* reflects number of current entries in RX FIFO */
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UART_VENDOR_STATE_TX_FIFO_COUNTER = 0b111111 << 24 /* reflects number of current entries in TX FIFO */
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} UartVendorStatus;
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/* 36.3.6 UART_LSR_0 */
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typedef enum {
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UART_LSR_RDR = 1 << 0, /* Receiver Data Ready */
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UART_LSR_OVRF = 1 << 1, /* Receiver Overrun Error */
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UART_LSR_PERR = 1 << 2, /* Parity Error */
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UART_LSR_FERR = 1 << 3, /* Framing Error */
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UART_LSR_BRK = 1 << 4, /* BREAK condition detected on line */
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UART_LSR_THRE = 1 << 5, /* Transmit Holding Register is Empty -- OK to write data */
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UART_LSR_TMTY = 1 << 6, /* Transmit Shift Register empty status */
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UART_LSR_FIFOE = 1 << 7, /* Receive FIFO Error */
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UART_LSR_TX_FIFO_FULL = 1 << 8, /* Transmitter FIFO full status */
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UART_LSR_RX_FIFO_EMPTY = 1 << 9, /* Receiver FIFO empty status */
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} UartLineStatus;
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/* 36.3.4 UART_LCR_0 */
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typedef enum {
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UART_LCR_WD_LENGTH_5 = 0, /* word length 5 */
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UART_LCR_WD_LENGTH_6 = 1, /* word length 6 */
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UART_LCR_WD_LENGTH_7 = 2, /* word length 7 */
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UART_LCR_WD_LENGTH_8 = 3, /* word length 8 */
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/* STOP:
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0 = Transmit 1 stop bit
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1 = Transmit 2 stop bits (receiver always checks for 1 stop bit)
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*/
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UART_LCR_STOP = 1 << 2,
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UART_LCR_PAR = 1 << 3, /* Parity enabled */
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UART_LCR_EVEN = 1 << 4, /* Even parity format. There will always be an even number of 1s in the binary representation (PAR = 1) */
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UART_LCR_SET_P = 1 << 5, /* Set (force) parity to value in LCR[4] */
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UART_LCR_SET_B = 1 << 6, /* Set BREAK condition -- Transmitter sends all zeroes to indicate BREAK */
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UART_LCR_DLAB = 1 << 7, /* Divisor Latch Access Bit (set to allow programming of the DLH, DLM Divisors) */
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} UartLineControl;
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/* 36.3.3 UART_IIR_FCR_0 */
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typedef enum {
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UART_FCR_FCR_EN_FIFO = 1 << 0, /* Enable the transmit and receive FIFOs. This bit should be enabled */
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UART_FCR_RX_CLR = 1 << 1, /* Clears the contents of the receive FIFO and resets its counter logic to 0 (the receive shift register is not cleared or altered). This bit returns to 0 after clearing the FIFOs */
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UART_FCR_TX_CLR = 1 << 2, /* Clears the contents of the transmit FIFO and resets its counter logic to 0 (the transmit shift register is not cleared or altered). This bit returns to 0 after clearing the FIFOs */
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/* DMA:
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0 = DMA_MODE_0
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1 = DMA_MODE_1
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*/
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UART_FCR_DMA = 1 << 3,
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/* TX_TRIG
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0 = FIFO_COUNT_GREATER_16
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1 = FIFO_COUNT_GREATER_8
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2 = FIFO_COUNT_GREATER_4
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3 = FIFO_COUNT_GREATER_1
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*/
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UART_FCR_TX_TRIG = 3 << 4,
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UART_FCR_TX_TRIG_FIFO_COUNT_GREATER_16 = 0 << 4,
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UART_FCR_TX_TRIG_FIFO_COUNT_GREATER_8 = 1 << 4,
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UART_FCR_TX_TRIG_FIFO_COUNT_GREATER_4 = 2 << 4,
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UART_FCR_TX_TRIG_FIFO_COUNT_GREATER_1 = 3 << 4,
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/* RX_TRIG
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0 = FIFO_COUNT_GREATER_1
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1 = FIFO_COUNT_GREATER_4
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2 = FIFO_COUNT_GREATER_8
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3 = FIFO_COUNT_GREATER_16
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*/
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UART_FCR_RX_TRIG = 3 << 6,
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UART_FCR_RX_TRIG_FIFO_COUNT_GREATER_1 = 0 << 6,
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UART_FCR_RX_TRIG_FIFO_COUNT_GREATER_4 = 1 << 6,
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UART_FCR_RX_TRIG_FIFO_COUNT_GREATER_8 = 2 << 6,
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UART_FCR_RX_TRIG_FIFO_COUNT_GREATER_16 = 3 << 6,
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} UartFifoControl;
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/* 36.3.3 UART_IIR_FCR_0 */
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typedef enum {
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UART_IIR_IS_STA = 1 << 0, /* Interrupt Pending if ZERO */
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UART_IIR_IS_PRI0 = 1 << 1, /* Encoded Interrupt ID Refer to IIR[3:0] table [36.3.3] */
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UART_IIR_IS_PRI1 = 1 << 2, /* Encoded Interrupt ID Refer to IIR[3:0] table */
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UART_IIR_IS_PRI2 = 1 << 3, /* Encoded Interrupt ID Refer to IIR[3:0] table */
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/* FIFO Mode Status
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0 = 16450 mode (no FIFO)
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1 = 16550 mode (FIFO)
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*/
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UART_IIR_EN_FIFO = 3 << 6,
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UART_IIR_MODE_16450 = 0 << 6,
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UART_IIR_MODE_16550 = 1 << 6,
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} UartInterruptIdentification;
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typedef struct {
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/* 0x00 */ uint32_t UART_THR_DLAB;
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/* 0x04 */ uint32_t UART_IER_DLAB;
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/* 0x08 */ uint32_t UART_IIR_FCR;
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/* 0x0C */ uint32_t UART_LCR;
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/* 0x10 */ uint32_t UART_MCR;
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/* 0x14 */ uint32_t UART_LSR;
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/* 0x18 */ uint32_t UART_MSR;
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/* 0x1C */ uint32_t UART_SPR;
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/* 0x20 */ uint32_t UART_IRDA_CSR;
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/* 0x24 */ uint32_t UART_RX_FIFO_CFG;
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/* 0x28 */ uint32_t UART_MIE;
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/* 0x2C */ uint32_t UART_VENDOR_STATUS;
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/* 0x30 */ uint8_t _pad_30[0x0C];
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/* 0x3C */ uint32_t UART_ASR;
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} uart_t;
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void uart_select(UartDevice dev);
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void uart_init(UartDevice dev, uint32_t baud);
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void uart_wait_idle(UartDevice dev, UartVendorStatus status);
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void uart_send(UartDevice dev, const void *buf, size_t len);
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void uart_recv(UartDevice dev, void *buf, size_t len);
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static inline volatile uart_t *get_uart_device(UartDevice dev) {
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static const size_t offsets[] = {0, 0x40, 0x200, 0x300, 0x400};
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return (volatile uart_t *)(UART_BASE + offsets[dev]);
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}
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#endif
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