mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
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116 lines
4.4 KiB
C++
116 lines
4.4 KiB
C++
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stratosphere.hpp>
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/* TODO: How much of this should be namespaced under BOARD_NINTENDO_NX? */
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namespace ams::wec {
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namespace {
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constexpr inline dd::PhysicalAddress ApbdevPmc = 0x7000E400;
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constinit bool g_initialized = false;
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void UpdateControlBit(dd::PhysicalAddress phys_addr, u32 mask, bool flag) {
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dd::ReadModifyWriteIoRegister(phys_addr, flag ? ~0u : 0u, mask);
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dd::ReadIoRegister(phys_addr);
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}
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void Initialize(bool blink) {
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/* Initialize WAKE_DEBOUNCE_EN. */
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dd::WriteIoRegister(ApbdevPmc + APBDEV_PMC_WAKE_DEBOUNCE_EN, 0);
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dd::ReadIoRegister(ApbdevPmc + APBDEV_PMC_WAKE_DEBOUNCE_EN);
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/* Initialize BLINK_TIMER. */
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dd::WriteIoRegister(ApbdevPmc + APBDEV_PMC_BLINK_TIMER, 0x08008800);
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dd::ReadIoRegister(ApbdevPmc + APBDEV_PMC_BLINK_TIMER);
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/* Set control configs. */
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UpdateControlBit(ApbdevPmc + APBDEV_PMC_CNTRL, 0x0800, true);
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UpdateControlBit(ApbdevPmc + APBDEV_PMC_CNTRL, 0x0400, false);
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UpdateControlBit(ApbdevPmc + APBDEV_PMC_CNTRL, 0x0200, true);
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UpdateControlBit(ApbdevPmc + APBDEV_PMC_CNTRL, 0x0100, false);
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UpdateControlBit(ApbdevPmc + APBDEV_PMC_CNTRL, 0x0040, false);
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UpdateControlBit(ApbdevPmc + APBDEV_PMC_CNTRL, 0x0020, false);
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UpdateControlBit(ApbdevPmc + APBDEV_PMC_CNTRL2, 0x4000, true);
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UpdateControlBit(ApbdevPmc + APBDEV_PMC_CNTRL2, 0x0200, false);
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UpdateControlBit(ApbdevPmc + APBDEV_PMC_CNTRL2, 0x0001, true);
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/* Update blink bit in APBDEV_PMC_CNTRL. */
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UpdateControlBit(ApbdevPmc + APBDEV_PMC_CNTRL, 0x0080, blink);
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/* Update blink bit in APBDEV_PMC_DPD_PADS_ORIDE. */
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UpdateControlBit(ApbdevPmc + APBDEV_PMC_DPD_PADS_ORIDE, 0x100000, blink);
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}
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}
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/* 0C, 160 */
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/* 10, 164 */
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/* DC, 170 */
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void Initialize() {
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/* Set initial wake configuration. */
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if (!g_initialized) {
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Initialize(false);
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g_initialized = true;
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}
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}
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void ClearWakeEvents() {
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/* TODO */
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AMS_ABORT();
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}
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void WecRestoreForExitSuspend() {
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/* TODO */
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AMS_ABORT();
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}
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void SetWakeEventLevel(wec::WakeEvent event, wec::WakeEventLevel level) {
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if (g_initialized && event < wec::WakeEvent_Count) {
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/* Determine the event index. */
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const bool which = static_cast<u32>(event) < BITSIZEOF(u32);
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const u32 index = static_cast<u32>(event) & (BITSIZEOF(u32) - 1);
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/* Get the level and auto_mask offsets. */
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u32 level_ofs = which ? APBDEV_PMC_WAKE_LVL : APBDEV_PMC_WAKE2_LVL;
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u32 auto_mask_ofs = which ? APBDEV_PMC_AUTO_WAKE_LVL_MASK : APBDEV_PMC_AUTO_WAKE2_LVL_MASK;
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/* If the level isn't auto, swap the offsets. */
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if (level != wec::WakeEventLevel_Auto) {
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std::swap(level_ofs, auto_mask_ofs);
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}
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/* Clear the bit in the level register. */
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UpdateControlBit(ApbdevPmc + level_ofs, (1u << index), false);
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/* Set or clear the bit in the auto mask register. */
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UpdateControlBit(ApbdevPmc + level_ofs, (1u << index), level != wec::WakeEventLevel_Low);
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}
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}
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void SetWakeEventEnabled(wec::WakeEvent event, bool en) {
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if (g_initialized && event < wec::WakeEvent_Count) {
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/* Set or clear the relevant enabled bit. */
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const u32 offset = static_cast<u32>(event) < BITSIZEOF(u32) ? APBDEV_PMC_WAKE_MASK : APBDEV_PMC_WAKE2_MASK;
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const u32 index = static_cast<u32>(event) & (BITSIZEOF(u32) - 1);
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UpdateControlBit(ApbdevPmc + offset, (1u << index), en);
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}
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}
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}
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