mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-11-23 12:22:08 +00:00
f66b41c027
exo2: Implement uncompressor stub and boot code up to Main(). exo2: implement some more init (uart/gic) exo2: implement more of init exo2: improve reg api, add keyslot flag setters exo2: implement se aes decryption/enc exo2: fix bugs in loader stub/mmu mappings exo2: start skeletoning bootconfig/global context types arch: fix makefile flags exo2: implement through master key derivation exo2: implement device master keygen exo2: more init through start of SetupSocSecurity exo2: implement pmc secure scratch management se: implement sticky bit validation libexosphere: fix building for arm32 libexo: fix makefile flags libexo: support building for arm64/arm sc7fw: skeleton binary sc7fw: skeleton a little more sc7fw: implement all non-dram functionality exo2: fix DivideUp error sc7fw: implement more dram code, fix reg library errors sc7fw: complete sc7fw impl. exo2: skeleton the rest of SetupSocSecurity exo2: implement fiq interrupt handler exo2: implement all exception handlers exo2: skeleton the entire smc api, implement the svc invoker exo2: implement rest of SetupSocSecurity exo2: correct slave security errors exo2: fix register definition exo2: minor fixes
279 lines
12 KiB
C++
279 lines
12 KiB
C++
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include <vapours.hpp>
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namespace ams::mmu::arch::arm64 {
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enum PageTableTableAttribute : u64 {
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PageTableTableAttribute_None = (0ul << 0),
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PageTableTableAttribute_PrivilegedExecuteNever = (1ul << 59),
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PageTableTableAttribute_ExecuteNever = (1ul << 60),
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PageTableTableAttribute_NonSecure = (1ul << 63),
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PageTableTableAttributes_El3SecureCode = PageTableTableAttribute_None,
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PageTableTableAttributes_El3SecureData = PageTableTableAttribute_ExecuteNever,
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PageTableTableAttributes_El3NonSecureCode = PageTableTableAttributes_El3SecureCode | PageTableTableAttribute_NonSecure,
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PageTableTableAttributes_El3NonSecureData = PageTableTableAttributes_El3SecureData | PageTableTableAttribute_NonSecure,
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};
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enum PageTableMappingAttribute : u64{
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/* Security. */
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PageTableMappingAttribute_NonSecure = (1ul << 5),
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/* El1 Access. */
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PageTableMappingAttribute_El1NotAllowed = (0ul << 6),
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PageTableMappingAttribute_El1Allowed = (1ul << 6),
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/* RW Permission. */
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PageTableMappingAttribute_PermissionReadWrite = (0ul << 7),
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PageTableMappingAttribute_PermissionReadOnly = (1ul << 7),
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/* Shareability. */
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PageTableMappingAttribute_ShareabilityNonShareable = (0ul << 8),
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PageTableMappingAttribute_ShareabiltiyOuterShareable = (2ul << 8),
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PageTableMappingAttribute_ShareabilityInnerShareable = (3ul << 8),
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/* Access flag. */
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PageTableMappingAttribute_AccessFlagNotAccessed = (0ul << 10),
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PageTableMappingAttribute_AccessFlagAccessed = (1ul << 10),
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/* Global. */
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PageTableMappingAttribute_Global = (0ul << 11),
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PageTableMappingAttribute_NonGlobal = (1ul << 11),
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/* Contiguous */
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PageTableMappingAttribute_NonContiguous = (0ul << 52),
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PageTableMappingAttribute_Contiguous = (1ul << 52),
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/* Privileged Execute Never */
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PageTableMappingAttribute_PrivilegedExecuteNever = (1ul << 53),
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/* Execute Never */
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PageTableMappingAttribute_ExecuteNever = (1ul << 54),
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/* Useful definitions. */
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PageTableMappingAttributes_El3SecureRwCode = (
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PageTableMappingAttribute_PermissionReadWrite |
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PageTableMappingAttribute_ShareabilityInnerShareable
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),
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PageTableMappingAttributes_El3SecureRoCode = (
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PageTableMappingAttribute_PermissionReadOnly |
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PageTableMappingAttribute_ShareabilityInnerShareable
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),
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PageTableMappingAttributes_El3SecureRoData = (
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PageTableMappingAttribute_PermissionReadOnly |
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PageTableMappingAttribute_ShareabilityInnerShareable |
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PageTableMappingAttribute_ExecuteNever
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),
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PageTableMappingAttributes_El3SecureRwData = (
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PageTableMappingAttribute_PermissionReadWrite |
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PageTableMappingAttribute_ShareabilityInnerShareable |
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PageTableMappingAttribute_ExecuteNever
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),
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PageTableMappingAttributes_El3NonSecureRwCode = PageTableMappingAttributes_El3SecureRwCode | PageTableMappingAttribute_NonSecure,
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PageTableMappingAttributes_El3NonSecureRoCode = PageTableMappingAttributes_El3SecureRoCode | PageTableMappingAttribute_NonSecure,
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PageTableMappingAttributes_El3NonSecureRoData = PageTableMappingAttributes_El3SecureRoData | PageTableMappingAttribute_NonSecure,
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PageTableMappingAttributes_El3NonSecureRwData = PageTableMappingAttributes_El3SecureRwData | PageTableMappingAttribute_NonSecure,
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PageTableMappingAttributes_El3SecureDevice = PageTableMappingAttributes_El3SecureRwData,
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PageTableMappingAttributes_El3NonSecureDevice = PageTableMappingAttributes_El3NonSecureRwData,
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};
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enum MemoryRegionAttribute : u64 {
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MemoryRegionAttribute_Device_nGnRnE = (0ul << 2),
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MemoryRegionAttribute_Device_nGnRE = (1ul << 2),
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MemoryRegionAttribute_NormalMemory = (2ul << 2),
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MemoryRegionAttribute_NormalMemoryNotCacheable = (3ul << 2),
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MemoryRegionAttribute_NormalInnerShift = 0,
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MemoryRegionAttribute_NormalOuterShift = 4,
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#define AMS_MRA_DEFINE_NORMAL_ATTR(__NAME__, __VAL__) \
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MemoryRegionAttribute_NormalInner##__NAME__ = (__VAL__ << MemoryRegionAttribute_NormalInnerShift), \
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MemoryRegionAttribute_NormalOuter##__NAME__ = (__VAL__ << MemoryRegionAttribute_NormalOuterShift)
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AMS_MRA_DEFINE_NORMAL_ATTR(NonCacheable, 4),
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AMS_MRA_DEFINE_NORMAL_ATTR(WriteAllocate, (1ul << 0)),
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AMS_MRA_DEFINE_NORMAL_ATTR(ReadAllocate, (1ul << 1)),
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AMS_MRA_DEFINE_NORMAL_ATTR(WriteThroughTransient, (0ul << 2)),
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AMS_MRA_DEFINE_NORMAL_ATTR(WriteBackTransient, (1ul << 2)),
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AMS_MRA_DEFINE_NORMAL_ATTR(WriteThroughNonTransient, (2ul << 2)),
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AMS_MRA_DEFINE_NORMAL_ATTR(WriteBackNonTransient, (3ul << 2)),
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#undef AMS_MRA_DEFINE_NORMAL_ATTR
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MemoryRegionAttributes_Normal = (
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MemoryRegionAttribute_NormalInnerReadAllocate |
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MemoryRegionAttribute_NormalOuterReadAllocate |
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MemoryRegionAttribute_NormalInnerWriteAllocate |
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MemoryRegionAttribute_NormalOuterWriteAllocate |
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MemoryRegionAttribute_NormalInnerWriteBackNonTransient |
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MemoryRegionAttribute_NormalOuterWriteBackNonTransient
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),
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MemoryRegionAttributes_Device = (
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MemoryRegionAttribute_Device_nGnRE
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),
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};
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constexpr inline u64 MemoryRegionAttributeWidth = 8;
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constexpr PageTableMappingAttribute AddMappingAttributeIndex(PageTableMappingAttribute attr, int index) {
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return static_cast<PageTableMappingAttribute>(attr | (static_cast<typename std::underlying_type<PageTableMappingAttribute>::type>(index) << 2));
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}
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constexpr inline u64 L1EntryShift = 30;
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constexpr inline u64 L2EntryShift = 21;
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constexpr inline u64 L3EntryShift = 12;
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constexpr inline u64 L1EntrySize = 1_GB;
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constexpr inline u64 L2EntrySize = 2_MB;
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constexpr inline u64 L3EntrySize = 4_KB;
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constexpr inline u64 PageSize = L3EntrySize;
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constexpr inline u64 L1EntryMask = ((1ul << (48 - L1EntryShift)) - 1) << L1EntryShift;
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constexpr inline u64 L2EntryMask = ((1ul << (48 - L2EntryShift)) - 1) << L2EntryShift;
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constexpr inline u64 L3EntryMask = ((1ul << (48 - L3EntryShift)) - 1) << L3EntryShift;
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constexpr inline u64 TableEntryMask = L3EntryMask;
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static_assert(L1EntryMask == 0x0000FFFFC0000000ul);
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static_assert(L2EntryMask == 0x0000FFFFFFE00000ul);
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static_assert(L3EntryMask == 0x0000FFFFFFFFF000ul);
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constexpr inline u64 TableEntryIndexMask = 0x1FF;
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constexpr inline u64 EntryBlock = 0x1ul;
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constexpr inline u64 EntryPage = 0x3ul;
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constexpr u64 MakeTableEntry(u64 address, PageTableTableAttribute attr) {
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return address | static_cast<u64>(attr) | 0x3ul;
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}
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constexpr u64 MakeL1BlockEntry(u64 address, PageTableMappingAttribute attr) {
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return address | static_cast<u64>(attr) | 0x1ul;
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}
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constexpr u64 MakeL2BlockEntry(u64 address, PageTableMappingAttribute attr) {
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return address | static_cast<u64>(attr) | 0x1ul;
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}
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constexpr u64 MakeL3BlockEntry(u64 address, PageTableMappingAttribute attr) {
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return address | static_cast<u64>(attr) | 0x3ul;
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}
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constexpr uintptr_t GetL2Offset(uintptr_t address) {
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return address & ((1ul << L2EntryShift) - 1);
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}
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constexpr u64 GetL1EntryIndex(uintptr_t address) {
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return ((address >> L1EntryShift) & TableEntryIndexMask);
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}
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constexpr u64 GetL2EntryIndex(uintptr_t address) {
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return ((address >> L2EntryShift) & TableEntryIndexMask);
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}
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constexpr u64 GetL3EntryIndex(uintptr_t address) {
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return ((address >> L3EntryShift) & TableEntryIndexMask);
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}
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constexpr ALWAYS_INLINE void SetTableImpl(u64 *table, u64 index, u64 value) {
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/* Ensure (for constexpr validation purposes) that the entry we set is clear. */
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if (table[index]) {
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__builtin_unreachable();
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}
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/* Set the value. */
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table[index] = value;
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}
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constexpr void SetL1TableEntry(u64 *table, uintptr_t virt_addr, uintptr_t phys_addr, PageTableTableAttribute attr) {
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SetTableImpl(table, GetL1EntryIndex(virt_addr), MakeTableEntry(phys_addr & TableEntryMask, attr));
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}
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constexpr void SetL2TableEntry(u64 *table, uintptr_t virt_addr, uintptr_t phys_addr, PageTableTableAttribute attr) {
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SetTableImpl(table, GetL2EntryIndex(virt_addr), MakeTableEntry(phys_addr & TableEntryMask, attr));
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}
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constexpr void SetL1BlockEntry(u64 *table, uintptr_t virt_addr, uintptr_t phys_addr, size_t size, PageTableMappingAttribute attr) {
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const u64 start = GetL1EntryIndex(virt_addr);
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const u64 count = (size >> L1EntryShift);
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for (u64 i = 0; i < count; ++i) {
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SetTableImpl(table, start + i, MakeL1BlockEntry((phys_addr & L1EntryMask) + (i << L1EntryShift), attr));
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}
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}
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constexpr void SetL2BlockEntry(u64 *table, uintptr_t virt_addr, uintptr_t phys_addr, size_t size, PageTableMappingAttribute attr) {
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const u64 start = GetL2EntryIndex(virt_addr);
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const u64 count = (size >> L2EntryShift);
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for (u64 i = 0; i < count; ++i) {
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SetTableImpl(table, start + i, MakeL2BlockEntry((phys_addr & L2EntryMask) + (i << L2EntryShift), attr));
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}
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}
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constexpr void SetL3BlockEntry(u64 *table, uintptr_t virt_addr, uintptr_t phys_addr, size_t size, PageTableMappingAttribute attr) {
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const u64 start = GetL3EntryIndex(virt_addr);
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const u64 count = (size >> L3EntryShift);
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for (u64 i = 0; i < count; ++i) {
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SetTableImpl(table, start + i, MakeL3BlockEntry((phys_addr & L3EntryMask) + (i << L3EntryShift), attr));
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}
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}
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constexpr void InvalidateL1Entries(u64 *table, uintptr_t virt_addr, size_t size) {
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const u64 start = GetL1EntryIndex(virt_addr);
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const u64 count = (size >> L1EntryShift);
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const u64 end = start + count;
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for (u64 i = start; i < end; ++i) {
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table[i] = 0;
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}
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}
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constexpr void InvalidateL2Entries(u64 *table, uintptr_t virt_addr, size_t size) {
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const u64 start = GetL2EntryIndex(virt_addr);
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const u64 count = (size >> L2EntryShift);
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const u64 end = start + count;
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for (u64 i = start; i < end; ++i) {
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table[i] = 0;
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}
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}
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constexpr void InvalidateL3Entries(u64 *table, uintptr_t virt_addr, size_t size) {
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const u64 start = GetL3EntryIndex(virt_addr);
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const u64 count = (size >> L3EntryShift);
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const u64 end = start + count;
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for (u64 i = start; i < end; ++i) {
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table[i] = 0;
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}
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}
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}
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