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54 lines
2.3 KiB
C
54 lines
2.3 KiB
C
#ifndef FUSEE_APB_MISC_H
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#define FUSEE_APB_MISC_H
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#define SDMMC1_PAD_CAL_DRVUP_SHIFT (20)
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#define SDMMC1_PAD_CAL_DRVDN_SHIFT (12)
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#define SDMMC1_PAD_CAL_DRVUP_MASK (0x7Fu << SDMMC1_PAD_CAL_DRVUP_SHIFT)
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#define SDMMC1_PAD_CAL_DRVDN_MASK (0x7Fu << SDMMC1_PAD_CAL_DRVDN_SHIFT)
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#define CFG2TMC_EMMC4_PAD_DRVUP_COMP_SHIFT (8)
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#define CFG2TMC_EMMC4_PAD_DRVDN_COMP_SHIFT (2)
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#define CFG2TMC_EMMC4_PAD_DRVUP_COMP_MASK (0x3Fu << CFG2TMC_EMMC4_PAD_DRVUP_COMP_SHIFT)
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#define CFG2TMC_EMMC4_PAD_DRVDN_COMP_MASK (0x3Fu << CFG2TMC_EMMC4_PAD_DRVDN_COMP_SHIFT)
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#define PADCTL_SDMMC1_DEEP_LOOPBACK (1 << 0)
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#define PADCTL_SDMMC3_DEEP_LOOPBACK (1 << 0)
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#define PADCTL_SDMMC2_ENABLE_DATA_IN (0xFF << 8)
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#define PADCTL_SDMMC2_ENABLE_CLK_IN (0x3 << 4)
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#define PADCTL_SDMMC2_DEEP_LOOPBACK (1 << 0)
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#define PADCTL_SDMMC4_ENABLE_DATA_IN (0xFF << 8)
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#define PADCTL_SDMMC4_ENABLE_CLK_IN (0x3 << 4)
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#define PADCTL_SDMMC4_DEEP_LOOPBACK (1 << 0)
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#define PADCTL_SDMMC1_CD_SOURCE (1 << 0)
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#define PADCTL_SDMMC1_WP_SOURCE (1 << 1)
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#define PADCTL_SDMMC3_CD_SOURCE (1 << 2)
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#define PADCTL_SDMMC3_WP_SOURCE (1 << 3)
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typedef struct {
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uint32_t asdbgreg; /* 0x810 */
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uint32_t reserved0[0x31];
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uint32_t sdmmc1_clk_lpbk_control; /* 0x8D4 */
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uint32_t sdmmc3_clk_lpbk_control; /* 0x8D8 */
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uint32_t emmc2_pad_cfg_control; /* 0x8DC */
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uint32_t emmc4_pad_cfg_control; /* 0x8E0 */
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uint32_t _todo0[0x6E];
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uint32_t sdmmc1_pad_cfgpadctrl; /* 0xA98 */
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uint32_t emmc2_pad_cfgpadctrl; /* 0xA9C */
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uint32_t emmc2_pad_drv_type_cfgpadctrl; /* 0xAA0 */
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uint32_t emmc2_pad_pupd_cfgpadctrl; /* 0xAA4 */
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uint32_t _todo1[0x03];
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uint32_t sdmmc3_pad_cfgpadctrl; /* 0xAB0 */
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uint32_t emmc4_pad_cfgpadctrl; /* 0xAB4 */
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uint32_t emmc4_pad_drv_type_cfgpadctrl; /* 0xAB8 */
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uint32_t emmc4_pad_pupd_cfgpadctrl; /* 0xABC */
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uint32_t _todo2[0x2E];
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uint32_t vgpio_gpio_mux_sel; /* 0xB74 */
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uint32_t qspi_sck_lpbk_control; /* 0xB78 */
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} tegra_padctl_t;
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static inline volatile tegra_padctl_t *padctl_get_regs(void)
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{
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return (volatile tegra_padctl_t *)0x70000810;
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}
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#endif
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