mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-11-08 21:21:48 +00:00
83 lines
3.7 KiB
C++
83 lines
3.7 KiB
C++
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <exosphere.hpp>
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namespace ams::flow {
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namespace {
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struct FlowControllerRegisterOffset {
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u16 cpu_csr;
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u16 halt_cpu_events;
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u16 cc4_core_ctrl;
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};
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constinit uintptr_t g_register_address = secmon::MemoryRegionPhysicalDeviceFlowController.GetAddress();
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constexpr const FlowControllerRegisterOffset FlowControllerRegisterOffsets[] = {
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{ FLOW_CTLR_CPU0_CSR, FLOW_CTLR_HALT_CPU0_EVENTS, FLOW_CTLR_CC4_CORE0_CTRL, },
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{ FLOW_CTLR_CPU1_CSR, FLOW_CTLR_HALT_CPU1_EVENTS, FLOW_CTLR_CC4_CORE1_CTRL, },
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{ FLOW_CTLR_CPU2_CSR, FLOW_CTLR_HALT_CPU2_EVENTS, FLOW_CTLR_CC4_CORE2_CTRL, },
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{ FLOW_CTLR_CPU3_CSR, FLOW_CTLR_HALT_CPU3_EVENTS, FLOW_CTLR_CC4_CORE3_CTRL, },
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};
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constexpr u32 GetHaltCpuEventsValue(bool resume_on_irq) {
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if (resume_on_irq) {
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return reg::Encode(FLOW_REG_BITS_ENUM(HALT_CPUN_EVENTS_FLOW_MODE, WAITEVENT),
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FLOW_REG_BITS_ENUM(HALT_CPUN_EVENTS_LIC_IRQN, ENABLE),
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FLOW_REG_BITS_ENUM(HALT_CPUN_EVENTS_LIC_FIQN, ENABLE),
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FLOW_REG_BITS_ENUM(HALT_CPUN_EVENTS_GIC_IRQN, ENABLE),
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FLOW_REG_BITS_ENUM(HALT_CPUN_EVENTS_GIC_FIQN, ENABLE));
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} else {
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return reg::Encode(FLOW_REG_BITS_ENUM(HALT_CPUN_EVENTS_FLOW_MODE, WAITEVENT));
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}
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}
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}
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void SetRegisterAddress(uintptr_t address) {
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g_register_address = address;
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}
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void ResetCpuRegisters(int core) {
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AMS_ASSUME(core >= 0);
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const auto &offsets = FlowControllerRegisterOffsets[core];
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reg::Write(g_register_address + offsets.cpu_csr, 0);
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reg::Write(g_register_address + offsets.halt_cpu_events, 0);
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}
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void SetCpuCsr(int core, u32 enable_ext) {
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reg::Write(g_register_address + FlowControllerRegisterOffsets[core].cpu_csr, FLOW_REG_BITS_ENUM (CPUN_CSR_INTR_FLAG, TRUE),
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FLOW_REG_BITS_ENUM (CPUN_CSR_EVENT_FLAG, TRUE),
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FLOW_REG_BITS_VALUE(CPUN_CSR_ENABLE_EXT, enable_ext),
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FLOW_REG_BITS_VALUE(CPUN_CSR_WAIT_WFI_BITMAP, (1u << core)),
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FLOW_REG_BITS_ENUM (CPUN_CSR_ENABLE, ENABLE));
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}
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void SetHaltCpuEvents(int core, bool resume_on_irq) {
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reg::Write(g_register_address + FlowControllerRegisterOffsets[core].halt_cpu_events, GetHaltCpuEventsValue(resume_on_irq));
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}
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void SetCc4Ctrl(int core, u32 value) {
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reg::Write(g_register_address + FlowControllerRegisterOffsets[core].cc4_core_ctrl, value);
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}
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void ClearL2FlushControl() {
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reg::Write(g_register_address + FLOW_CTLR_L2FLUSH_CONTROL, 0);
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}
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}
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