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94 lines
2.7 KiB
ArmAsm
94 lines
2.7 KiB
ArmAsm
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* For some reason GAS doesn't know about it, even with .cpu cortex-a57 */
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#define cpuactlr_el1 s3_1_c15_c2_0
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#define cpuectlr_el1 s3_1_c15_c2_1
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.section .text._ZN3ams6secmon3smc19PivotStackAndInvokeEPvPFvvE, "ax", %progbits
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.align 4
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.global _ZN3ams6secmon3smc19PivotStackAndInvokeEPvPFvvE
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_ZN3ams6secmon3smc19PivotStackAndInvokeEPvPFvvE:
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/* Pivot to use the provided stack pointer. */
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mov sp, x0
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/* Release our lock on the common smc stack. */
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mov x19, x1
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bl _ZN3ams6secmon25ReleaseCommonSmcStackLockEv
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/* Invoke the function with the new stack. */
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br x19
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.section .text._ZN3ams6secmon3smc16FinalizePowerOffEv, "ax", %progbits
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.align 4
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.global _ZN3ams6secmon3smc16FinalizePowerOffEv
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_ZN3ams6secmon3smc16FinalizePowerOffEv:
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/* Disable all caches by clearing sctlr_el1.C. */
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mrs x0, sctlr_el1
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and x0, x0, #~(1 << 2)
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msr sctlr_el1, x0
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isb
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/* Disable all caches by clearing sctlr_el3.C. */
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mrs x0, sctlr_el3
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and x0, x0, #~(1 << 2)
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msr sctlr_el3, x0
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isb
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/* Disable prefetching of page table walking descriptors. */
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mrs x0, cpuectlr_el1
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orr x0, x0, #(1 << 38)
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/* Disable prefetching of instructions. */
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and x0, x0, #~(3 << 35)
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/* Disable prefetching of data. */
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and x0, x0, #~(3 << 32)
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msr cpuectlr_el1, x0
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isb
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/* Ensure that all data prefetching prior to our configuration change completes. */
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dsb sy
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/* Flush the entire data cache (local). */
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bl _ZN3ams6secmon25FlushEntireDataCacheLocalEv
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/* Disable receiving instruction cache/TLB maintenance operations. */
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mrs x0, cpuectlr_el1
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and x0, x0, #~(1 << 6)
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msr cpuectlr_el1, x0
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/* Configure the gic to not send interrupts to the current core. */
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ldr x1, =0x1F0043000
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mov w0, #0x1E0 /* Set FIQBypDisGrp1, IRQBypDisGrp1, reserved bits 7/8. */
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str w0, [x1]
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/* Lock the OS Double Lock. */
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mrs x0, osdlr_el1
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orr x0, x0, #(1 << 0)
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msr osdlr_el1, x0
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/* Ensure that our configuration takes. */
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isb
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dsb sy
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/* Wait for interrupts, infinitely. */
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0:
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wfi
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b 0b
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