mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-12-22 18:32:05 +00:00
352 lines
15 KiB
C++
352 lines
15 KiB
C++
/*
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* Copyright (c) Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <exosphere.hpp>
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namespace ams::secmon::fatal {
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namespace {
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/* Definitions. */
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constexpr size_t PageDirectorySize = mmu::PageSize;
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constexpr size_t PageTableSize = mmu::PageSize;
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static_assert(PageDirectorySize == mmu::PageSize);
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using DeviceVirtualAddress = u64;
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constexpr size_t AsidCount = 0x80;
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constexpr size_t PhysicalAddressBits = 34;
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constexpr size_t PhysicalAddressMask = (1ul << PhysicalAddressBits) - 1ul;
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constexpr size_t DeviceVirtualAddressBits = 34;
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constexpr size_t DeviceVirtualAddressMask = (1ul << DeviceVirtualAddressBits) - 1ul;
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constexpr size_t DevicePageBits = 12;
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constexpr size_t DevicePageSize = (1ul << DevicePageBits);
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static_assert(DevicePageSize == mmu::PageSize);
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constexpr size_t DeviceLargePageBits = 22;
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constexpr size_t DeviceLargePageSize = (1ul << DeviceLargePageBits);
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static_assert(DeviceLargePageSize % DevicePageSize == 0);
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constexpr size_t DeviceRegionBits = 32;
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constexpr size_t DeviceRegionSize = (1ul << DeviceRegionBits);
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static_assert(DeviceRegionSize % DeviceLargePageSize == 0);
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constexpr const uintptr_t MC = secmon::MemoryRegionVirtualDeviceMemoryController.GetAddress();
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constexpr size_t TableCount = (1ul << DeviceVirtualAddressBits) / DeviceRegionSize;
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consteval u32 EncodeAsidRegisterValue(u8 asid) {
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u32 value = 0x80000000u;
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for (size_t t = 0; t < TableCount; t++) {
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value |= (asid << (BITSIZEOF(u8) * t));
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}
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return value;
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}
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constexpr u8 SdmmcAsid = 1;
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constexpr u8 DcAsid = 2;
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constexpr u32 SdmmcAsidRegisterValue = EncodeAsidRegisterValue(SdmmcAsid);
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constexpr u32 DcAsidRegisterValue = EncodeAsidRegisterValue(DcAsid);
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constexpr dd::PhysicalAddress DcL0PageTablePhysical = MemoryRegionPhysicalDramDcL0DevicePageTable.GetAddress();
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constexpr dd::PhysicalAddress SdmmcL0PageTablePhysical = MemoryRegionPhysicalDramSdmmc1L0DevicePageTable.GetAddress();
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constexpr dd::PhysicalAddress SdmmcL1PageTablePhysical = MemoryRegionPhysicalDramSdmmc1L1DevicePageTable.GetAddress();
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/* Types. */
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class EntryBase {
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protected:
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enum Bit : u32 {
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Bit_Table = 28,
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Bit_NonSecure = 29,
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Bit_Writeable = 30,
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Bit_Readable = 31,
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};
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private:
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u32 m_value;
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protected:
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constexpr ALWAYS_INLINE u32 SelectBit(Bit n) const {
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return (m_value & (1u << n));
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}
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constexpr ALWAYS_INLINE bool GetBit(Bit n) const {
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return this->SelectBit(n) != 0;
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}
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static constexpr ALWAYS_INLINE u32 EncodeBit(Bit n, bool en) {
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return en ? (1u << n) : 0;
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}
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static constexpr ALWAYS_INLINE u32 EncodeValue(bool r, bool w, bool ns, dd::PhysicalAddress addr, bool t) {
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return EncodeBit(Bit_Readable, r) | EncodeBit(Bit_Writeable, w) | EncodeBit(Bit_NonSecure, ns) | EncodeBit(Bit_Table, t) | static_cast<u32>(addr >> DevicePageBits);
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}
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ALWAYS_INLINE void SetValue(u32 v) {
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/* Prevent re-ordering around entry modifications. */
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__asm__ __volatile__("" ::: "memory");
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m_value = v;
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__asm__ __volatile__("" ::: "memory");
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}
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public:
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static constexpr ALWAYS_INLINE u32 EncodePtbDataValue(dd::PhysicalAddress addr) {
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return EncodeValue(true, true, true, addr, false);
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}
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public:
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constexpr ALWAYS_INLINE bool IsNonSecure() const { return this->GetBit(Bit_NonSecure); }
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constexpr ALWAYS_INLINE bool IsWriteable() const { return this->GetBit(Bit_Writeable); }
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constexpr ALWAYS_INLINE bool IsReadable() const { return this->GetBit(Bit_Readable); }
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constexpr ALWAYS_INLINE bool IsValid() const { return this->IsWriteable() || this->IsReadable(); }
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constexpr ALWAYS_INLINE u32 GetAttributes() const { return this->SelectBit(Bit_NonSecure) | this->SelectBit(Bit_Writeable) | this->SelectBit(Bit_Readable); }
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constexpr ALWAYS_INLINE dd::PhysicalAddress GetPhysicalAddress() const { return (static_cast<u64>(m_value) << DevicePageBits) & PhysicalAddressMask; }
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ALWAYS_INLINE void Invalidate() { this->SetValue(0); }
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};
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class PageDirectoryEntry : public EntryBase {
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public:
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constexpr ALWAYS_INLINE bool IsTable() const { return this->GetBit(Bit_Table); }
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ALWAYS_INLINE void SetTable(bool r, bool w, bool ns, dd::PhysicalAddress addr) {
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AMS_ASSERT(util::IsAligned(addr, DevicePageSize));
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this->SetValue(EncodeValue(r, w, ns, addr, true));
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}
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ALWAYS_INLINE void SetLargePage(bool r, bool w, bool ns, dd::PhysicalAddress addr) {
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AMS_ASSERT(util::IsAligned(addr, DeviceLargePageSize));
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this->SetValue(EncodeValue(r, w, ns, addr, false));
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}
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};
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class PageTableEntry : public EntryBase {
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public:
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ALWAYS_INLINE void SetPage(bool r, bool w, bool ns, dd::PhysicalAddress addr) {
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AMS_ASSERT(util::IsAligned(addr, DevicePageSize));
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this->SetValue(EncodeValue(r, w, ns, addr, true));
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}
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};
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/* Memory controller access functionality. */
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void WriteMcRegister(size_t offset, u32 value) {
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reg::Write(MC + offset, value);
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}
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u32 ReadMcRegister(size_t offset) {
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return reg::Read(MC + offset);
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}
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/* Memory controller utilities. */
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void SmmuSynchronizationBarrier() {
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ReadMcRegister(MC_SMMU_CONFIG);
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}
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void InvalidatePtc() {
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WriteMcRegister(MC_SMMU_PTC_FLUSH_0, 0);
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}
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void InvalidatePtc(dd::PhysicalAddress address) {
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WriteMcRegister(MC_SMMU_PTC_FLUSH_1, (static_cast<u64>(address) >> 32));
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WriteMcRegister(MC_SMMU_PTC_FLUSH_0, (address & 0xFFFFFFF0u) | 1u);
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}
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enum TlbFlushVaMatch : u32 {
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TlbFlushVaMatch_All = 0,
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TlbFlushVaMatch_Section = 2,
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TlbFlushVaMatch_Group = 3,
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};
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static constexpr ALWAYS_INLINE u32 EncodeTlbFlushValue(bool match_asid, u8 asid, dd::PhysicalAddress address, TlbFlushVaMatch match) {
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return ((match_asid ? 1u : 0u) << 31) | ((asid & 0x7F) << 24) | (((address & 0xFFC00000u) >> DevicePageBits)) | (match);
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}
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void InvalidateTlb() {
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return WriteMcRegister(MC_SMMU_TLB_FLUSH, EncodeTlbFlushValue(false, 0, 0, TlbFlushVaMatch_All));
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}
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void InvalidateTlb(u8 asid) {
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return WriteMcRegister(MC_SMMU_TLB_FLUSH, EncodeTlbFlushValue(true, asid, 0, TlbFlushVaMatch_All));
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}
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void InvalidateTlbSection(u8 asid, dd::PhysicalAddress address) {
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return WriteMcRegister(MC_SMMU_TLB_FLUSH, EncodeTlbFlushValue(true, asid, address, TlbFlushVaMatch_Section));
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}
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void SetTable(u8 asid, dd::PhysicalAddress address) {
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/* Write the table address. */
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{
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WriteMcRegister(MC_SMMU_PTB_ASID, asid);
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WriteMcRegister(MC_SMMU_PTB_DATA, EntryBase::EncodePtbDataValue(address));
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SmmuSynchronizationBarrier();
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}
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/* Ensure consistency. */
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InvalidatePtc();
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InvalidateTlb(asid);
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SmmuSynchronizationBarrier();
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}
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void MapImpl(dd::PhysicalAddress phys_addr, size_t size, DeviceVirtualAddress address, u8 asid, void *l0_table, dd::PhysicalAddress l0_phys, void *l1_table, dd::PhysicalAddress l1_phys) {
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/* Validate L0. */
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AMS_ABORT_UNLESS(l0_table != nullptr);
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AMS_ABORT_UNLESS(l0_phys != 0);
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/* Cache permissions. */
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const bool read = true;
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const bool write = true;
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/* Walk the directory. */
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u64 remaining = size;
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while (remaining > 0) {
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const size_t l1_index = (address % DeviceRegionSize) / DeviceLargePageSize;
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const size_t l2_index = (address % DeviceLargePageSize) / DevicePageSize;
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/* Get and validate l1. */
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PageDirectoryEntry *l1 = static_cast<PageDirectoryEntry *>(l0_table);
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AMS_ASSERT(l1 != nullptr);
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/* Setup an l1 table/entry, if needed. */
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if (!l1[l1_index].IsTable()) {
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/* Check that an entry doesn't already exist. */
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AMS_ASSERT(!l1[l1_index].IsValid());
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/* If we can make an l1 entry, do so. */
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if (l2_index == 0 && util::IsAligned(phys_addr, DeviceLargePageSize) && remaining >= DeviceLargePageSize) {
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/* Set the large page. */
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l1[l1_index].SetLargePage(read, write, true, phys_addr);
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hw::FlushDataCache(std::addressof(l1[l1_index]), sizeof(PageDirectoryEntry));
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/* Synchronize. */
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InvalidatePtc(l0_phys + l1_index * sizeof(PageDirectoryEntry));
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InvalidateTlbSection(asid, address);
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SmmuSynchronizationBarrier();
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/* Advance. */
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phys_addr += DeviceLargePageSize;
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address += DeviceLargePageSize;
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remaining -= DeviceLargePageSize;
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continue;
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} else {
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/* Make an l1 table. */
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AMS_ABORT_UNLESS(l1_table != nullptr);
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AMS_ABORT_UNLESS(l1_phys != 0);
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/* Clear the l1 table. */
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std::memset(l1_table, 0, mmu::PageSize);
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hw::FlushDataCache(l1_table, mmu::PageSize);
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/* Set the l1 table. */
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l1[l1_index].SetTable(true, true, true, l1_phys);
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hw::FlushDataCache(std::addressof(l1[l1_index]), sizeof(PageDirectoryEntry));
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/* Synchronize. */
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InvalidatePtc(l0_phys + l1_index * sizeof(PageDirectoryEntry));
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InvalidateTlbSection(asid, address);
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SmmuSynchronizationBarrier();
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}
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}
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/* If we get to this point, l1 must be a table. */
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AMS_ASSERT(l1[l1_index].IsTable());
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AMS_ABORT_UNLESS(l1_table != nullptr);
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AMS_ABORT_UNLESS(l1_phys != 0);
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/* Map l2 entries. */
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{
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PageTableEntry *l2 = static_cast<PageTableEntry *>(l1_table);
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const size_t remaining_in_entry = (PageTableSize / sizeof(PageTableEntry)) - l2_index;
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const size_t map_count = std::min<size_t>(remaining_in_entry, remaining / DevicePageSize);
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/* Set the entries. */
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for (size_t i = 0; i < map_count; ++i) {
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AMS_ASSERT(!l2[l2_index + i].IsValid());
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l2[l2_index + i].SetPage(read, write, true, phys_addr + DevicePageSize * i);
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}
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hw::FlushDataCache(std::addressof(l2[l2_index]), map_count * sizeof(PageTableEntry));
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/* Invalidate the page table cache. */
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for (size_t i = util::AlignDown(l2_index, 4); i <= util::AlignDown(l2_index + map_count - 1, 4); i += 4) {
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InvalidatePtc(l1_phys + i * sizeof(PageTableEntry));
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}
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/* Synchronize. */
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InvalidateTlbSection(asid, address);
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SmmuSynchronizationBarrier();
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/* Advance. */
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phys_addr += map_count * DevicePageSize;
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address += map_count * DevicePageSize;
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remaining -= map_count * DevicePageSize;
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}
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}
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}
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}
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void InitializeDevicePageTableForSdmmc1() {
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/* Configure sdmmc to use our new page table. */
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WriteMcRegister(MC_SMMU_SDMMC1A_ASID, SdmmcAsidRegisterValue);
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SmmuSynchronizationBarrier();
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/* Ensure consistency. */
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InvalidatePtc();
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InvalidateTlb();
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SmmuSynchronizationBarrier();
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/* Clear the L0 Page Table. */
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std::memset(MemoryRegionVirtualDramSdmmc1L0DevicePageTable.GetPointer<void>(), 0, mmu::PageSize);
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hw::FlushDataCache(MemoryRegionVirtualDramSdmmc1L0DevicePageTable.GetPointer<void>(), mmu::PageSize);
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/* Set the page table for the sdmmc asid. */
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SetTable(SdmmcAsid, SdmmcL0PageTablePhysical);
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/* Map the appropriate region into the asid. */
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MapImpl(MemoryRegionPhysicalDramSdmmcMappedData.GetAddress(), MemoryRegionPhysicalDramSdmmcMappedData.GetSize(), MemoryRegionVirtualDramSdmmcMappedData.GetAddress(),
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SdmmcAsid,
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MemoryRegionVirtualDramSdmmc1L0DevicePageTable.GetPointer<void>(), SdmmcL0PageTablePhysical,
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MemoryRegionVirtualDramSdmmc1L1DevicePageTable.GetPointer<void>(), SdmmcL1PageTablePhysical);
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}
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void InitializeDevicePageTableForDc() {
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/* Configure dc to use our new page table. */
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WriteMcRegister(MC_SMMU_DC_ASID, DcAsidRegisterValue);
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SmmuSynchronizationBarrier();
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/* Ensure consistency. */
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InvalidatePtc();
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InvalidateTlb();
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SmmuSynchronizationBarrier();
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/* Clear the L0 Page Table. */
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std::memset(MemoryRegionVirtualDramDcL0DevicePageTable.GetPointer<void>(), 0, mmu::PageSize);
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hw::FlushDataCache(MemoryRegionVirtualDramDcL0DevicePageTable.GetPointer<void>(), mmu::PageSize);
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/* Set the page table for the dc asid. */
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SetTable(DcAsid, DcL0PageTablePhysical);
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/* Map the appropriate region into the asid. */
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static_assert(util::IsAligned(MemoryRegionDramDcFramebuffer.GetAddress(), DeviceLargePageSize));
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static_assert(util::IsAligned(MemoryRegionDramDcFramebuffer.GetSize(), DeviceLargePageSize));
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MapImpl(MemoryRegionDramDcFramebuffer.GetAddress(), MemoryRegionDramDcFramebuffer.GetSize(), MemoryRegionDramDcFramebuffer.GetAddress(),
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DcAsid,
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MemoryRegionVirtualDramDcL0DevicePageTable.GetPointer<void>(), DcL0PageTablePhysical,
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nullptr, 0);
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}
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}
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