mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
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f66b41c027
exo2: Implement uncompressor stub and boot code up to Main(). exo2: implement some more init (uart/gic) exo2: implement more of init exo2: improve reg api, add keyslot flag setters exo2: implement se aes decryption/enc exo2: fix bugs in loader stub/mmu mappings exo2: start skeletoning bootconfig/global context types arch: fix makefile flags exo2: implement through master key derivation exo2: implement device master keygen exo2: more init through start of SetupSocSecurity exo2: implement pmc secure scratch management se: implement sticky bit validation libexosphere: fix building for arm32 libexo: fix makefile flags libexo: support building for arm64/arm sc7fw: skeleton binary sc7fw: skeleton a little more sc7fw: implement all non-dram functionality exo2: fix DivideUp error sc7fw: implement more dram code, fix reg library errors sc7fw: complete sc7fw impl. exo2: skeleton the rest of SetupSocSecurity exo2: implement fiq interrupt handler exo2: implement all exception handlers exo2: skeleton the entire smc api, implement the svc invoker exo2: implement rest of SetupSocSecurity exo2: correct slave security errors exo2: fix register definition exo2: minor fixes
138 lines
5.5 KiB
C++
138 lines
5.5 KiB
C++
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <exosphere.hpp>
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#include "se_execute.hpp"
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namespace ams::se {
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namespace {
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struct LinkedListEntry {
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u32 zero;
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u32 address;
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u32 size;
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};
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static_assert(util::is_pod<LinkedListEntry>::value);
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uintptr_t GetPhysicalAddress(const void *ptr) {
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const uintptr_t virt_address = reinterpret_cast<uintptr_t>(ptr);
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#if defined(ATMOSPHERE_ARCH_ARM64)
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u64 phys_address;
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__asm__ __volatile__("at s1e3r, %[virt]; mrs %[phys], par_el1" : [phys]"=r"(phys_address) : [virt]"r"(virt_address) : "memory", "cc");
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return (phys_address & 0x0000FFFFFFFFF000ul) | (virt_address & 0x0000000000000FFFul);
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#elif defined(ATMOSPHERE_ARCH_ARM)
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return virt_address;
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#else
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#error "Unknown architecture for Tegra Security Engine physical address translation"
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#endif
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}
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constexpr void SetLinkedListEntry(LinkedListEntry *entry, const void *ptr, size_t size) {
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/* Clear the zero field. */
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entry->zero = 0;
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/* Set the address. */
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if (ptr != nullptr) {
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entry->address = GetPhysicalAddress(ptr);
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entry->size = static_cast<u32>(size);
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} else {
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entry->address = 0;
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entry->size = 0;
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}
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}
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void StartOperation(volatile SecurityEngineRegisters *SE, SE_OPERATION_OP op) {
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/* Write back the current values of the error and interrupt status. */
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reg::Write(SE->SE_ERR_STATUS, reg::Read(SE->SE_ERR_STATUS));
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reg::Write(SE->SE_INT_STATUS, reg::Read(SE->SE_INT_STATUS));
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/* Write the operation. */
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reg::Write(SE->SE_OPERATION, SE_REG_BITS_VALUE(OPERATION_OP, op));
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}
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void WaitForOperationComplete(volatile SecurityEngineRegisters *SE) {
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/* Spin until the operation is done. */
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while (reg::HasValue(SE->SE_INT_STATUS, SE_REG_BITS_ENUM(INT_STATUS_SE_OP_DONE, CLEAR))) { /* ... */ }
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/* Check for operation success. */
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ValidateAesOperationResult(SE);
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}
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}
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void ExecuteOperation(volatile SecurityEngineRegisters *SE, SE_OPERATION_OP op, void *dst, size_t dst_size, const void *src, size_t src_size) {
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/* Set the linked list entries. */
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LinkedListEntry src_entry;
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LinkedListEntry dst_entry;
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SetLinkedListEntry(std::addressof(src_entry), src, src_size);
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SetLinkedListEntry(std::addressof(dst_entry), dst, dst_size);
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/* Ensure the linked list entry data is seen correctly. */
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hw::FlushDataCache(std::addressof(src_entry), sizeof(src_entry));
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hw::FlushDataCache(std::addressof(dst_entry), sizeof(dst_entry));
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hw::DataSynchronizationBarrierInnerShareable();
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/* Configure the linked list addresses. */
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reg::Write(SE->SE_IN_LL_ADDR, static_cast<u32>(GetPhysicalAddress(std::addressof(src_entry))));
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reg::Write(SE->SE_OUT_LL_ADDR, static_cast<u32>(GetPhysicalAddress(std::addressof(dst_entry))));
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/* Start the operation. */
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StartOperation(SE, op);
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/* Wait for the operation to complete. */
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WaitForOperationComplete(SE);
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}
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void ExecuteOperationSingleBlock(volatile SecurityEngineRegisters *SE, void *dst, size_t dst_size, const void *src, size_t src_size) {
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/* Validate sizes. */
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AMS_ABORT_UNLESS(dst_size <= AesBlockSize);
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AMS_ABORT_UNLESS(src_size == AesBlockSize);
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/* Set the block count to 1. */
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reg::Write(SE->SE_CRYPTO_LAST_BLOCK, 0);
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/* Create an aligned buffer. */
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util::AlignedBuffer<hw::DataCacheLineSize, AesBlockSize> aligned;
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std::memcpy(aligned, src, AesBlockSize);
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hw::FlushDataCache(aligned, AesBlockSize);
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hw::DataSynchronizationBarrierInnerShareable();
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/* Execute the operation. */
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ExecuteOperation(SE, SE_OPERATION_OP_START, aligned, AesBlockSize, aligned, AesBlockSize);
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/* Ensure that the CPU will see the correct output. */
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hw::DataSynchronizationBarrierInnerShareable();
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hw::FlushDataCache(aligned, AesBlockSize);
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hw::DataSynchronizationBarrierInnerShareable();
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/* Copy the output to the destination. */
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std::memcpy(dst, aligned, dst_size);
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}
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void ValidateAesOperationResult(volatile SecurityEngineRegisters *SE) {
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/* Ensure no error occurred. */
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AMS_ABORT_UNLESS(reg::HasValue(SE->SE_INT_STATUS, SE_REG_BITS_ENUM(INT_STATUS_ERR_STAT, CLEAR)));
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/* Ensure the security engine is idle. */
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AMS_ABORT_UNLESS(reg::HasValue(SE->SE_STATUS, SE_REG_BITS_ENUM(STATUS_STATE, IDLE)));
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/* Ensure there is no error status. */
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AMS_ABORT_UNLESS(reg::Read(SE->SE_ERR_STATUS) == 0);
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}
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}
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