mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
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263 lines
7.7 KiB
C
263 lines
7.7 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdint.h>
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#include "cluster.h"
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#include "flow.h"
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#include "sysreg.h"
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#include "i2c.h"
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#include "car.h"
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#include "fuse.h"
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#include "mc.h"
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#include "timers.h"
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#include "pmc.h"
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#include "max77620.h"
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#include "max77812.h"
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/* Determine the current SoC for Mariko specific code. */
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static bool is_soc_mariko() {
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return (fuse_get_soc_type() == 1);
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}
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static void cluster_enable_power(uint32_t regulator) {
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switch (regulator) {
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case 0: /* Regulator_Max77621 */
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uint8_t val = 0;
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i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
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val &= 0xDF;
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i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
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val = 0x09;
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i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_GPIO5, &val, 1);
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val = 0x20;
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i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x02, &val, 1);
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val = 0x8D;
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i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x03, &val, 1);
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val = 0xB7;
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i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x00, &val, 1);
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val = 0xB7;
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i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x01, &val, 1);
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break;
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case 1: /* Regulator_Max77812PhaseConfiguration31 */
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uint8_t val = 0;
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i2c_query(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
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if (val) {
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val |= 0x40;
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i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
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}
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val = 0x6E;
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i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
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break;
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case 2: /* Regulator_Max77812PhaseConfiguration211 */
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uint8_t val = 0;
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i2c_query(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
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if (val) {
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val |= 0x40;
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i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
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}
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val = 0x6E;
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i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
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break;
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default: return;
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}
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}
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static void cluster_pmc_enable_partition(uint32_t part, uint32_t toggle) {
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volatile tegra_pmc_t *pmc = pmc_get_regs();
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/* Check if the partition has already been turned on. */
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if (pmc->pwrgate_status & part) {
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return;
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}
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uint32_t i = 5001;
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while (pmc->pwrgate_toggle & 0x100) {
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udelay(1);
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i--;
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if (i < 1) {
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return;
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}
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}
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/* Turn the partition on. */
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pmc->pwrgate_toggle = (toggle | 0x100);
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i = 5001;
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while (i > 0) {
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/* Check if the partition has already been turned on. */
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if (pmc->pwrgate_status & part) {
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break;
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}
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udelay(1);
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i--;
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}
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}
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static void cluster_boot_cpu0_erista(uint32_t entry) {
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volatile tegra_car_t *car = car_get_regs();
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/* Set ACTIVE_CLUSER to FAST. */
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FLOW_CTLR_BPMP_CLUSTER_CONTROL_0 &= 0xFFFFFFFE;
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/* Enable VddCpu. */
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cluster_enable_power(0);
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if (!(car->pllx_base & 0x40000000)) {
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car->pllx_misc3 &= 0xFFFFFFF7;
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udelay(2);
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car->pllx_base = 0x80404E02;
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car->pllx_base = 0x404E02;
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car->pllx_misc = ((car->pllx_misc & 0xFFFBFFFF) | 0x40000);
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car->pllx_base = 0x40404E02;
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}
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while (!(car->pllx_base & 0x8000000)) {
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/* Wait. */
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}
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/* Configure MSELECT source and enable clock. */
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car->clk_source_mselect = ((car->clk_source_mselect & 0x1FFFFF00) | 6);
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car->clk_out_enb_v = ((car->clk_out_enb_v & 0xFFFFFFF7) | 8);
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/* Configure initial CPU clock frequency and enable clock. */
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car->cclk_brst_pol = 0x20008888;
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car->super_cclk_div = 0x80000000;
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car->clk_enb_v_set = 1;
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clkrst_reboot(CARDEVICE_CORESIGHT);
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/* CAR2PMC_CPU_ACK_WIDTH should be set to 0. */
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car->cpu_softrst_ctrl2 &= 0xFFFFF000;
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/* Enable CPU rail. */
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cluster_pmc_enable_partition(1, 0);
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/* Enable cluster 0 non-CPU. */
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cluster_pmc_enable_partition(0x8000, 15);
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/* Enable CE0. */
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cluster_pmc_enable_partition(0x4000, 14);
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/* Request and wait for RAM repair. */
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FLOW_CTLR_RAM_REPAIR_0 = 1;
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while (!(FLOW_CTLR_RAM_REPAIR_0 & 2)) {
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/* Wait. */
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}
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MAKE_EXCP_VEC_REG(0x100) = 0;
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/* Set reset vector. */
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SB_AA64_RESET_LOW_0 = (entry | 1);
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SB_AA64_RESET_HIGH_0 = 0;
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/* Non-secure reset vector write disable. */
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SB_CSR_0 = 2;
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(void)SB_CSR_0;
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/* Set CPU_STRICT_TZ_APERTURE_CHECK. */
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/* NOTE: [4.0.0+] This was added, but it breaks Exosphère. */
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/* MAKE_MC_REG(MC_TZ_SECURITY_CTRL) = 1; */
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/* Clear MSELECT reset. */
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car->rst_dev_v &= 0xFFFFFFF7;
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/* Clear NONCPU reset. */
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car->rst_cpug_cmplx_clr = 0x20000000;
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/* Clear CPU{0,1,2,3} POR and CORE, CX0, L2, and DBG reset.*/
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/* NOTE: [5.0.0+] This was changed so only CPU0 reset is cleared. */
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/* car->rst_cpug_cmplx_clr = 0x411F000F; */
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car->rst_cpug_cmplx_clr = 0x41010001;
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}
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static void cluster_boot_cpu0_mariko(uint32_t entry) {
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volatile tegra_car_t *car = car_get_regs();
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/* Set ACTIVE_CLUSER to FAST. */
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FLOW_CTLR_BPMP_CLUSTER_CONTROL_0 &= 0xFFFFFFFE;
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/* Enable VddCpu. */
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cluster_enable_power(fuse_get_regulator());
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if (!(car->pllx_base & 0x40000000)) {
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car->pllx_misc3 &= 0xFFFFFFF7;
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udelay(2);
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car->pllx_misc = ((car->pllx_misc & 0xFFFBFFFF) | 0x40000);
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car->pllx_base = 0x40404E02;
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}
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while (!(car->pllx_base & 0x8000000)) {
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/* Wait. */
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}
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/* Set MSELECT clock. */
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clk_enable(CARDEVICE_MSELECT);
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/* Configure initial CPU clock frequency and enable clock. */
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car->cclk_brst_pol = 0x20008888;
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car->super_cclk_div = 0x80000000;
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car->clk_enb_v_set = 1;
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/* Reboot CORESIGHT. */
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clkrst_reboot(CARDEVICE_CORESIGHT);
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/* Set CAR2PMC_CPU_ACK_WIDTH to 0. */
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car->cpu_softrst_ctrl2 &= 0xFFFFF000;
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/* Enable CPU rail. */
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cluster_pmc_enable_partition(1, 0);
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/* Enable cluster 0 non-CPU. */
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cluster_pmc_enable_partition(0x8000, 15);
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/* Enable CE0. */
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cluster_pmc_enable_partition(0x4000, 14);
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/* Request and wait for RAM repair. */
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FLOW_CTLR_RAM_REPAIR_0 = 1;
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while (!(FLOW_CTLR_RAM_REPAIR_0 & 2)) {
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/* Wait. */
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}
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MAKE_EXCP_VEC_REG(0x100) = 0;
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/* Set reset vector. */
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SB_AA64_RESET_LOW_0 = (entry | 1);
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SB_AA64_RESET_HIGH_0 = 0;
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/* Non-secure reset vector write disable. */
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SB_CSR_0 = 2;
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(void)SB_CSR_0;
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/* Set CPU_STRICT_TZ_APERTURE_CHECK. */
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/* NOTE: This breaks Exosphère. */
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/* MAKE_MC_REG(MC_TZ_SECURITY_CTRL) = 1; */
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/* Clear MSELECT reset. */
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rst_disable(CARDEVICE_MSELECT);
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/* Clear CPU{0,1,2,3} POR and CORE, CX0, L2, and DBG reset.*/
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car->rst_cpug_cmplx_clr = 0x41010001;
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}
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void cluster_boot_cpu0(uint32_t entry) {
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if (is_soc_mariko()) {
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cluster_boot_cpu0_mariko(uint32_t entry);
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} else {
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cluster_boot_cpu0_erista(uint32_t entry);
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}
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}
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