mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-11-08 21:21:48 +00:00
354 lines
16 KiB
C++
354 lines
16 KiB
C++
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <exosphere.hpp>
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#include "se_execute.hpp"
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namespace ams::se {
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namespace {
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constexpr inline size_t SE1ContextSaveOperationCount = 133;
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constexpr inline size_t SE2ContextSaveOperationCount = 646;
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static_assert(((SE1ContextSaveOperationCount - 2) + 1) * se::AesBlockSize == sizeof(se::Context));
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constinit const u8 FixedPattern[AesBlockSize] = {
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0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F
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};
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bool TestRegister(volatile u32 &r, u16 v) {
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return (static_cast<u16>(reg::Read(r))) == v;
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}
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void ExecuteContextSaveOperation(volatile SecurityEngineRegisters *SE, void *dst, size_t dst_size, const void *src, size_t src_size) {
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/* Save the output to a temporary buffer. */
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util::AlignedBuffer<hw::DataCacheLineSize, AesBlockSize> temp;
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AMS_ABORT_UNLESS(dst_size <= AesBlockSize);
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/* Ensure that the cpu and SE see consistent data. */
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if (src_size > 0) {
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hw::FlushDataCache(src, src_size);
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hw::DataSynchronizationBarrierInnerShareable();
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}
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if (dst_size > 0) {
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hw::FlushDataCache(temp, AesBlockSize);
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hw::DataSynchronizationBarrierInnerShareable();
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}
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/* Execute the operation. */
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ExecuteOperation(SE, SE_OPERATION_OP_CTX_SAVE, temp, dst_size, src, src_size);
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/* Copy output from the operation, if any. */
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if (dst_size > 0) {
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hw::DataSynchronizationBarrierInnerShareable();
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hw::FlushDataCache(temp, AesBlockSize);
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hw::DataSynchronizationBarrierInnerShareable();
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std::memcpy(dst, temp, dst_size);
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}
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}
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void SaveContextBlock(volatile SecurityEngineRegisters *SE, void *dst) {
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/* Configure to encrypt a single block. */
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reg::Write(SE->SE_CRYPTO_LAST_BLOCK, 0);
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/* Execute the operation. */
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ExecuteContextSaveOperation(SE, dst, AesBlockSize, nullptr, 0);
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}
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void ConfigureForAutomaticContextSave(volatile SecurityEngineRegisters *SE) {
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/* Configure the engine to do RNG encryption. */
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reg::Write(SE->SE_CONFIG, SE_REG_BITS_ENUM(CONFIG_ENC_MODE, AESMODE_KEY128),
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SE_REG_BITS_ENUM(CONFIG_DEC_MODE, AESMODE_KEY128),
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SE_REG_BITS_ENUM(CONFIG_ENC_ALG, RNG),
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SE_REG_BITS_ENUM(CONFIG_DEC_ALG, NOP),
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SE_REG_BITS_ENUM(CONFIG_DST, MEMORY));
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reg::Write(SE->SE_CRYPTO_CONFIG, SE_REG_BITS_ENUM (CRYPTO_CONFIG_MEMIF, AHB),
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SE_REG_BITS_VALUE(CRYPTO_CONFIG_CTR_CNTN, 0),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_KEYSCH_BYPASS, DISABLE),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_CORE_SEL, ENCRYPT),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_IV_SELECT, ORIGINAL),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_VCTRAM_SEL, MEMORY),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_INPUT_SEL, RANDOM),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_XOR_POS, BYPASS),
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SE_REG_BITS_ENUM (CRYPTO_CONFIG_HASH_ENB, DISABLE));
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}
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void WaitAutomaticContextSaveDone(volatile SecurityEngineRegisters *SE) {
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/* Wait for operation. */
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while (!reg::HasValue(SE->SE_INT_STATUS, SE_REG_BITS_ENUM(INT_STATUS_SE_OP_DONE, ACTIVE))) { /* ... */ }
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/* Wait for the engine to be idle. */
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while (!reg::HasValue(SE->SE_STATUS, SE_REG_BITS_ENUM(STATUS_STATE, IDLE))) { /* ... */ }
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/* Wait for the memory interface to be idle. */
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while (!reg::HasValue(SE->SE_STATUS, SE_REG_BITS_ENUM(STATUS_MEM_INTERFACE, IDLE))) { /* ... */ }
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}
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void ValidateErrStatus(volatile SecurityEngineRegisters *SE) {
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/* Ensure there is no error status. */
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AMS_ABORT_UNLESS(reg::Read(SE->SE_ERR_STATUS) == 0);
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/* Ensure no error occurred. */
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AMS_ABORT_UNLESS(reg::HasValue(SE->SE_INT_STATUS, SE_REG_BITS_ENUM(INT_STATUS_ERR_STAT, CLEAR)));
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}
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}
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bool ValidateStickyBits(const StickyBits &bits) {
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/* Get the registers. */
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auto *SE = GetRegisters();
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/* Check SE_SECURITY. */
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if (!TestRegister(SE->SE_SE_SECURITY, bits.se_security)) { return false; }
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/* Check TZRAM_SECURITY. */
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if (!TestRegister(SE->SE_TZRAM_SECURITY, bits.tzram_security)) { return false; }
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/* Check CRYPTO_SECURITY_PERKEY. */
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if (!TestRegister(SE->SE_CRYPTO_SECURITY_PERKEY, bits.crypto_security_perkey)) { return false; }
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/* Check CRYPTO_KEYTABLE_ACCESS. */
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for (int i = 0; i < AesKeySlotCount; ++i) {
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if (!TestRegister(SE->SE_CRYPTO_KEYTABLE_ACCESS[i], bits.crypto_keytable_access[i])) { return false; }
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}
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/* Test RSA_SECURITY_PERKEY */
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if (!TestRegister(SE->SE_RSA_SECURITY_PERKEY, bits.rsa_security_perkey)) { return false; }
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/* Check RSA_KEYTABLE_ACCESS. */
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for (int i = 0; i < RsaKeySlotCount; ++i) {
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if (!TestRegister(SE->SE_RSA_KEYTABLE_ACCESS[i], bits.rsa_keytable_access[i])) { return false; }
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}
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/* All sticky bits are valid. */
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return true;
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}
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void SaveContext(Context *dst) {
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/* Get the registers. */
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auto *SE = GetRegisters();
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/* Generate a random srk. */
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GenerateSrk();
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/* Save a randomly-generated block. */
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{
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util::AlignedBuffer<hw::DataCacheLineSize, AesBlockSize> random_block;
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/* Flush the region we're about to fill to ensure consistency with the SE. */
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hw::FlushDataCache(random_block, AesBlockSize);
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hw::DataSynchronizationBarrierInnerShareable();
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/* Generate random bytes. */
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GenerateRandomBytes(random_block, AesBlockSize);
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hw::DataSynchronizationBarrierInnerShareable();
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/* Flush to ensure the CPU sees consistent data for the region. */
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hw::FlushDataCache(random_block, AesBlockSize);
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hw::DataSynchronizationBarrierInnerShareable();
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/* Configure to encrypt the random block to memory. */
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reg::Write(SE->SE_CONFIG, SE_REG_BITS_ENUM(CONFIG_ENC_MODE, AESMODE_KEY128),
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SE_REG_BITS_ENUM(CONFIG_DEC_MODE, AESMODE_KEY128),
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SE_REG_BITS_ENUM(CONFIG_ENC_ALG, AES_ENC),
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SE_REG_BITS_ENUM(CONFIG_DEC_ALG, NOP),
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SE_REG_BITS_ENUM(CONFIG_DST, MEMORY));
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/* Configure to context save using memory as source. */
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reg::Write(SE->SE_CTX_SAVE_CONFIG, SE_REG_BITS_ENUM(CTX_SAVE_CONFIG_SRC, MEM));
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/* Configure to encrypt a single block. */
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reg::Write(SE->SE_CRYPTO_LAST_BLOCK, 0);
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/* Execute the operation. */
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ExecuteContextSaveOperation(SE, dst->random, AesBlockSize, random_block, AesBlockSize);
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}
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/* Save the sticky bits. */
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for (size_t i = 0; i < util::size(dst->sticky_bits); ++i) {
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/* Configure to encrypt the sticky bits block. */
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reg::Write(SE->SE_CTX_SAVE_CONFIG, SE_REG_BITS_ENUM (CTX_SAVE_CONFIG_SRC, STICKY_BITS),
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SE_REG_BITS_VALUE(CTX_SAVE_CONFIG_STICKY_WORD_QUAD, i));
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/* Save the block. */
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SaveContextBlock(SE, dst->sticky_bits[i]);
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}
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/* Save the aes keytable. */
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{
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for (size_t key = 0; key < util::size(dst->aes_key); ++key) {
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for (auto part = 0; part < AesKeySlotPartCount; ++part) {
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/* Configure to encrypt the part of the key. */
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reg::Write(SE->SE_CTX_SAVE_CONFIG, SE_REG_BITS_ENUM (CTX_SAVE_CONFIG_SRC, AES_KEYTABLE),
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SE_REG_BITS_VALUE(CTX_SAVE_CONFIG_AES_KEY_INDEX, key),
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SE_REG_BITS_VALUE(CTX_SAVE_CONFIG_AES_WORD_QUAD, part));
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/* Save the block. */
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SaveContextBlock(SE, dst->aes_key[key][part]);
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}
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}
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for (size_t key = 0; key < util::size(dst->aes_oiv); ++key) {
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/* Configure to encrypt the original iv. */
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reg::Write(SE->SE_CTX_SAVE_CONFIG, SE_REG_BITS_ENUM (CTX_SAVE_CONFIG_SRC, AES_KEYTABLE),
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SE_REG_BITS_VALUE(CTX_SAVE_CONFIG_AES_KEY_INDEX, key),
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SE_REG_BITS_ENUM (CTX_SAVE_CONFIG_AES_WORD_QUAD, ORIGINAL_IVS));
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/* Save the block. */
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SaveContextBlock(SE, dst->aes_oiv[key]);
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}
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for (size_t key = 0; key < util::size(dst->aes_uiv); ++key) {
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/* Configure to encrypt the updated iv. */
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reg::Write(SE->SE_CTX_SAVE_CONFIG, SE_REG_BITS_ENUM (CTX_SAVE_CONFIG_SRC, AES_KEYTABLE),
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SE_REG_BITS_VALUE(CTX_SAVE_CONFIG_AES_KEY_INDEX, key),
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SE_REG_BITS_ENUM (CTX_SAVE_CONFIG_AES_WORD_QUAD, UPDATED_IVS));
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/* Save the block. */
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SaveContextBlock(SE, dst->aes_uiv[key]);
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}
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}
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/* Save the rsa keytable. */
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for (size_t key = 0; key < util::size(dst->rsa_key); ++key) {
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for (auto part = 0; part < RsaKeySlotPartCount; ++part) {
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/* Note that the parts are done in reverse order. */
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const auto part_index = RsaKeySlotPartCount - 1 - part;
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/* Determine a total key index. */
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const auto key_index = key * util::size(dst->rsa_key) + part_index;
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for (size_t block = 0; block < RsaSize / AesBlockSize; ++block) {
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/* Configure to encrypt the part of the key. */
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reg::Write(SE->SE_CTX_SAVE_CONFIG, SE_REG_BITS_ENUM (CTX_SAVE_CONFIG_SRC, RSA_KEYTABLE),
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SE_REG_BITS_VALUE(CTX_SAVE_CONFIG_RSA_KEY_INDEX, key_index),
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SE_REG_BITS_VALUE(CTX_SAVE_CONFIG_RSA_WORD_QUAD, block));
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/* Save the block. */
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SaveContextBlock(SE, dst->rsa_key[key][part][block]);
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}
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}
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}
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/* Save the fixed pattern. */
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{
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/* Configure to context save using memory as source. */
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reg::Write(SE->SE_CTX_SAVE_CONFIG, SE_REG_BITS_ENUM(CTX_SAVE_CONFIG_SRC, MEM));
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/* Configure to encrypt a single block. */
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reg::Write(SE->SE_CRYPTO_LAST_BLOCK, 0);
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/* Execute the operation. */
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ExecuteContextSaveOperation(SE, dst->fixed_pattern, AesBlockSize, FixedPattern, AesBlockSize);
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}
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/* Save the srk. */
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{
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/* Configure to context save using srk as source. */
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reg::Write(SE->SE_CTX_SAVE_CONFIG, SE_REG_BITS_ENUM(CTX_SAVE_CONFIG_SRC, SRK));
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/* Configure to encrypt a single block. */
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reg::Write(SE->SE_CRYPTO_LAST_BLOCK, 0);
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/* Execute the operation. */
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ExecuteContextSaveOperation(SE, nullptr, 0, nullptr, 0);
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}
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/* Perform a no-op context save operation. */
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{
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/* Configure to perform no-op. */
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reg::Write(SE->SE_CONFIG, SE_REG_BITS_ENUM(CONFIG_ENC_ALG, NOP),
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SE_REG_BITS_ENUM(CONFIG_DEC_ALG, NOP));
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/* Execute the operation. */
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ExecuteContextSaveOperation(SE, nullptr, 0, nullptr, 0);
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}
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}
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void ConfigureAutomaticContextSave() {
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/* Get registers. */
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auto *SE = GetRegisters();
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auto *SE2 = GetRegisters2();
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/* Automatic context save is supported only on mariko. */
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if (fuse::GetSocType() == fuse::SocType_Mariko) {
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/* Configure SE1 to do automatic context save. */
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reg::Write(SE->SE_CTX_SAVE_AUTO, SE_REG_BITS_ENUM(CTX_SAVE_AUTO_ENABLE, YES),
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SE_REG_BITS_ENUM(CTX_SAVE_AUTO_LOCK, YES));
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/* Configure SE2 to do automatic context save. */
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reg::Write(SE2->SE_CTX_SAVE_AUTO, SE_REG_BITS_ENUM(CTX_SAVE_AUTO_ENABLE, YES),
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SE_REG_BITS_ENUM(CTX_SAVE_AUTO_LOCK, YES));
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}
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}
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void SaveContextAutomatic() {
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/* Get registers. */
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auto *SE = GetRegisters();
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auto *SE2 = GetRegisters2();
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/* Ensure there's no error status before or after we save context. */
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ValidateErrStatus();
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ON_SCOPE_EXIT { ValidateErrStatus(); };
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/* Perform atomic context save. */
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{
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/* Check that context save has not already been performed. */
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AMS_ABORT_UNLESS(reg::HasValue(SE->SE_CTX_SAVE_AUTO, SE_REG_BITS_VALUE(CTX_SAVE_AUTO_CURR_CNT, 0)));
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AMS_ABORT_UNLESS(reg::HasValue(SE2->SE_CTX_SAVE_AUTO, SE_REG_BITS_VALUE(CTX_SAVE_AUTO_CURR_CNT, 0)));
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/* Configure SE1 to do context save. */
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ConfigureForAutomaticContextSave(SE);
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ConfigureForAutomaticContextSave(SE2);
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/* Start the context save operation. */
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reg::Write(SE->SE_OPERATION, SE_REG_BITS_ENUM(OPERATION_OP, CTX_SAVE));
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reg::Write(SE2->SE_OPERATION, SE_REG_BITS_ENUM(OPERATION_OP, CTX_SAVE));
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/* Wait for the context save operation to complete. */
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WaitAutomaticContextSaveDone(SE);
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WaitAutomaticContextSaveDone(SE2);
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/* Check that the correct sizes were written. */
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AMS_ABORT_UNLESS(reg::HasValue(SE->SE_CTX_SAVE_AUTO, SE_REG_BITS_VALUE(CTX_SAVE_AUTO_CURR_CNT, SE1ContextSaveOperationCount)));
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AMS_ABORT_UNLESS(reg::HasValue(SE2->SE_CTX_SAVE_AUTO, SE_REG_BITS_VALUE(CTX_SAVE_AUTO_CURR_CNT, SE2ContextSaveOperationCount)));
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}
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}
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void SaveTzramAutomatic() {
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/* Get registers. */
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auto *SE = GetRegisters();
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/* Begin save-to-shadow-tzram operation. */
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reg::Write(SE->SE_TZRAM_OPERATION, SE_REG_BITS_ENUM(TZRAM_OPERATION_MODE, SAVE),
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SE_REG_BITS_ENUM(TZRAM_OPERATION_REQ, INITIATE));
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/* Wait for operation to complete. */
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while (reg::HasValue(SE->SE_TZRAM_OPERATION, SE_REG_BITS_ENUM(TZRAM_OPERATION_BUSY, YES))) { /* ... */ }
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}
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void ValidateErrStatus() {
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/* Ensure SE has no error status. */
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ValidateErrStatus(GetRegisters());
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/* If on mariko, ensure SE2 has no error status. */
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if (fuse::GetSocType() == fuse::SocType_Mariko) {
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ValidateErrStatus(GetRegisters2());
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}
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}
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}
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