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79 lines
2 KiB
ArmAsm
79 lines
2 KiB
ArmAsm
.align 6
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.section .text.warm.start, "ax", %progbits
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.global __start_warm
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__start_warm:
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/* Nintendo copy-pasted https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/nvidia/tegra/common/aarch64/tegra_helpers.S#L312 */
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/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* The following comments are mine. */
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/* mask all interrupts */
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msr daifset, daif
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/*
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Enable invalidates of branch target buffer, then flush
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the entire instruction cache at the local level, and
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with the reg change, the branch target buffer, then disable
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invalidates of the branch target buffer again.
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*/
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mrs x0, cpuactlr_el1
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orr x0, x0, #1
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msr cpuactlr_el1, x0
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dsb sy
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isb
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ic iallu
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dsb sy
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isb
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mrs x0, cpuactlr_el1
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bic x0, x0, #1
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msr cpuactlr_el1, x0
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.rept 7
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nop /* wait long enough for the write to cpuactlr_el1 to have completed */
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.endr
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/* if the OS lock is set, disable it and request a warm reset */
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mrs x0, oslsr_el1
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ands x0, x0, #2
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b.eq _set_lock_and_sp
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mov x0, xzr
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msr oslar_el1, x0
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mov x0, #(1 << 63)
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msr cpuactlr_el1, x0 /* disable regional clock gating */
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isb
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mov x0, #3
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msr rmr_el3, x0
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isb
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dsb sy
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/* Nintendo forgot to copy-paste the branch instruction below. */
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_reset_wfi:
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wfi
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b _reset_wfi
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.rept 65
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nop /* guard against speculative excecution */
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.endr
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_set_lock_and_sp:
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/* set the OS lock */
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mov x0, #1
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msr oslar_el1, x0
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bl __synchronize_cores
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/* set SP = SP_EL3 (handler stack) */
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msr spsel, #1
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ldr x20, =__warm_crt0_stack_top__
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mov sp, x20
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bl reconfigure_memory
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ldr x16, =__init_warm
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br x16
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.section .text.warm, "ax", %progbits
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__init_warm:
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ldr x20, =__warm_init_stack_top__
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mov sp, x20
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b warmboot_main
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