mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-12-29 21:56:04 +00:00
ee9585dd57
subrepo: subdir: "emummc" merged: "25075973" upstream: origin: "https://github.com/m4xw/emuMMC" branch: "develop" commit: "25075973" git-subrepo: version: "0.4.1" origin: "???" commit: "???"
446 lines
11 KiB
C
446 lines
11 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2020 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "../soc/clock.h"
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#include "../soc/t210.h"
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#include "../utils/util.h"
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#include "../emmc/sdmmc.h"
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static const sclock_t _clock_i2c5 = {
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CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, 0xF, 0, 4 //81.6MHz -> 400KHz
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};
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static sclock_t _clock_sdmmc_legacy_tm = {
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CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM, 1, 4, 66
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};
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void clock_enable(const sclock_t *clk)
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{
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// Put clock into reset.
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CLOCK(clk->reset) = (CLOCK(clk->reset) & ~(1 << clk->index)) | (1 << clk->index);
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// Disable.
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CLOCK(clk->enable) &= ~(1 << clk->index);
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// Configure clock source if required.
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if (clk->source)
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CLOCK(clk->source) = clk->clk_div | (clk->clk_src << 29);
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// Enable.
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CLOCK(clk->enable) = (CLOCK(clk->enable) & ~(1 << clk->index)) | (1 << clk->index);
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usleep(2);
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// Take clock off reset.
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CLOCK(clk->reset) &= ~(1 << clk->index);
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}
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void clock_disable(const sclock_t *clk)
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{
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// Put clock into reset.
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CLOCK(clk->reset) = (CLOCK(clk->reset) & ~(1 << clk->index)) | (1 << clk->index);
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// Disable.
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CLOCK(clk->enable) &= ~(1 << clk->index);
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}
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void clock_enable_i2c5()
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{
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clock_enable(&_clock_i2c5);
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}
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void clock_disable_i2c5()
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{
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clock_disable(&_clock_i2c5);
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}
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static void _clock_enable_pllc4()
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{
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if ((CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) & (PLLCX_BASE_ENABLE | PLLCX_BASE_LOCK | 0xFFFFFF))
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== (PLLCX_BASE_ENABLE | PLLCX_BASE_LOCK | (104 << 8) | 4))
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return;
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// Enable Phase and Frequency lock detection.
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//CLOCK(CLK_RST_CONTROLLER_PLLC4_MISC) = PLLC4_MISC_EN_LCKDET;
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// Disable PLL and IDDQ in case they are on.
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CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) &= ~PLLCX_BASE_ENABLE;
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CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) &= ~PLLC4_BASE_IDDQ;
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(void)CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE);
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usleep(10);
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// Set PLLC4 dividers.
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CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) = (104 << 8) | 4; // DIVM: 4, DIVP: 1.
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// Enable PLLC4 and wait for Phase and Frequency lock.
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CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) |= PLLCX_BASE_ENABLE;
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(void)CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE);
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while (!(CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) & PLLCX_BASE_LOCK))
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;
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msleep(1); // Wait a bit for PLL to stabilize.
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}
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#define L_SWR_SDMMC1_RST (1 << 14)
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#define L_SWR_SDMMC2_RST (1 << 9)
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#define L_SWR_SDMMC4_RST (1 << 15)
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#define U_SWR_SDMMC3_RST (1 << 5)
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#define L_CLK_ENB_SDMMC1 (1 << 14)
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#define L_CLK_ENB_SDMMC2 (1 << 9)
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#define L_CLK_ENB_SDMMC4 (1 << 15)
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#define U_CLK_ENB_SDMMC3 (1 << 5)
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#define L_SET_SDMMC1_RST (1 << 14)
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#define L_SET_SDMMC2_RST (1 << 9)
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#define L_SET_SDMMC4_RST (1 << 15)
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#define U_SET_SDMMC3_RST (1 << 5)
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#define L_CLR_SDMMC1_RST (1 << 14)
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#define L_CLR_SDMMC2_RST (1 << 9)
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#define L_CLR_SDMMC4_RST (1 << 15)
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#define U_CLR_SDMMC3_RST (1 << 5)
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#define L_SET_CLK_ENB_SDMMC1 (1 << 14)
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#define L_SET_CLK_ENB_SDMMC2 (1 << 9)
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#define L_SET_CLK_ENB_SDMMC4 (1 << 15)
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#define U_SET_CLK_ENB_SDMMC3 (1 << 5)
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#define L_CLR_CLK_ENB_SDMMC1 (1 << 14)
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#define L_CLR_CLK_ENB_SDMMC2 (1 << 9)
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#define L_CLR_CLK_ENB_SDMMC4 (1 << 15)
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#define U_CLR_CLK_ENB_SDMMC3 (1 << 5)
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static int _clock_sdmmc_is_reset(u32 id)
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{
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switch (id)
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{
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case SDMMC_1:
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return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_L) & L_SWR_SDMMC1_RST;
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case SDMMC_2:
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return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_L) & L_SWR_SDMMC2_RST;
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case SDMMC_3:
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return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_U) & U_SWR_SDMMC3_RST;
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case SDMMC_4:
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return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_L) & L_SWR_SDMMC4_RST;
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}
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return 0;
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}
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static void _clock_sdmmc_set_reset(u32 id)
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{
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switch (id)
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{
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case SDMMC_1:
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = L_SET_SDMMC1_RST;
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break;
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case SDMMC_2:
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = L_SET_SDMMC2_RST;
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break;
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case SDMMC_3:
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_U_SET) = U_SET_SDMMC3_RST;
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break;
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case SDMMC_4:
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = L_SET_SDMMC4_RST;
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break;
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}
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}
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static void _clock_sdmmc_clear_reset(u32 id)
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{
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switch (id)
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{
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case SDMMC_1:
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = L_CLR_SDMMC1_RST;
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break;
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case SDMMC_2:
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = L_CLR_SDMMC2_RST;
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break;
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case SDMMC_3:
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_U_CLR) = U_CLR_SDMMC3_RST;
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break;
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case SDMMC_4:
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = L_CLR_SDMMC4_RST;
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break;
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}
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}
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static int _clock_sdmmc_is_enabled(u32 id)
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{
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switch (id)
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{
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case SDMMC_1:
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return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & L_CLK_ENB_SDMMC1;
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case SDMMC_2:
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return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & L_CLK_ENB_SDMMC2;
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case SDMMC_3:
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return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_U) & U_CLK_ENB_SDMMC3;
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case SDMMC_4:
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return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & L_CLK_ENB_SDMMC4;
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}
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return 0;
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}
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static void _clock_sdmmc_set_enable(u32 id)
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{
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switch (id)
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{
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case SDMMC_1:
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = L_SET_CLK_ENB_SDMMC1;
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break;
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case SDMMC_2:
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = L_SET_CLK_ENB_SDMMC2;
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break;
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case SDMMC_3:
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_U_SET) = U_SET_CLK_ENB_SDMMC3;
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break;
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case SDMMC_4:
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = L_SET_CLK_ENB_SDMMC4;
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break;
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}
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}
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static void _clock_sdmmc_clear_enable(u32 id)
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{
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switch (id)
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{
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case SDMMC_1:
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = L_CLR_CLK_ENB_SDMMC1;
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break;
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case SDMMC_2:
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = L_CLR_CLK_ENB_SDMMC2;
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break;
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case SDMMC_3:
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_U_CLR) = U_CLR_CLK_ENB_SDMMC3;
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break;
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case SDMMC_4:
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = L_CLR_CLK_ENB_SDMMC4;
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break;
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}
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}
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static void _clock_sdmmc_config_legacy_tm()
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{
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sclock_t *clk = &_clock_sdmmc_legacy_tm;
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if (!(CLOCK(clk->enable) & (1 << clk->index)))
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clock_enable(clk);
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}
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typedef struct _clock_sdmmc_t
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{
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u32 clock;
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u32 real_clock;
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} clock_sdmmc_t;
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static clock_sdmmc_t _clock_sdmmc_table[4] = { 0 };
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#define SDMMC_CLOCK_SRC_PLLP_OUT0 0x0
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#define SDMMC_CLOCK_SRC_PLLC4_OUT2 0x3
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#define SDMMC4_CLOCK_SRC_PLLC4_OUT2_LJ 0x1
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static int _clock_sdmmc_config_clock_host(u32 *pclock, u32 id, u32 val)
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{
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u32 divisor = 0;
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u32 source = SDMMC_CLOCK_SRC_PLLP_OUT0;
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if (id > SDMMC_4)
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return 0;
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// Get IO clock divisor.
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switch (val)
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{
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case 25000:
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*pclock = 24728;
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divisor = 31; // 16.5 div.
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break;
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case 26000:
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*pclock = 25500;
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divisor = 30; // 16 div.
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break;
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case 40800:
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*pclock = 40800;
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divisor = 18; // 10 div.
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break;
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case 50000:
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*pclock = 48000;
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divisor = 15; // 8.5 div.
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break;
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case 52000:
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*pclock = 51000;
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divisor = 14; // 8 div.
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break;
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case 100000:
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source = SDMMC_CLOCK_SRC_PLLC4_OUT2;
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*pclock = 99840;
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divisor = 2; // 2 div.
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break;
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case 164000:
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*pclock = 163200;
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divisor = 3; // 2.5 div.
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break;
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case 200000:
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switch (id)
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{
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case SDMMC_1:
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source = SDMMC_CLOCK_SRC_PLLC4_OUT2;
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break;
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case SDMMC_2:
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source = SDMMC4_CLOCK_SRC_PLLC4_OUT2_LJ;
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break;
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case SDMMC_3:
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source = SDMMC_CLOCK_SRC_PLLC4_OUT2;
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break;
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case SDMMC_4:
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source = SDMMC4_CLOCK_SRC_PLLC4_OUT2_LJ;
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break;
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}
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*pclock = 199680;
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divisor = 0; // 1 div.
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break;
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default:
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*pclock = 24728;
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divisor = 31; // 16.5 div.
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}
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_clock_sdmmc_table[id].clock = val;
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_clock_sdmmc_table[id].real_clock = *pclock;
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// PLLC4 and LEGACY_TM clocks are already initialized,
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// because we init at the first eMMC read.
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// // Enable PLLC4 if in use by any SDMMC.
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// if (source)
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// _clock_enable_pllc4();
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// // Set SDMMC legacy timeout clock.
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// _clock_sdmmc_config_legacy_tm();
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// Set SDMMC clock.
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switch (id)
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{
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case SDMMC_1:
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1) = (source << 29) | divisor;
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break;
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case SDMMC_2:
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2) = (source << 29) | divisor;
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break;
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case SDMMC_3:
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3) = (source << 29) | divisor;
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break;
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case SDMMC_4:
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4) = (source << 29) | divisor;
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break;
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}
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return 1;
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}
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void clock_sdmmc_config_clock_source(u32 *pclock, u32 id, u32 val)
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{
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if (_clock_sdmmc_table[id].clock == val)
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{
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*pclock = _clock_sdmmc_table[id].real_clock;
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}
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else
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{
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int is_enabled = _clock_sdmmc_is_enabled(id);
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if (is_enabled)
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_clock_sdmmc_clear_enable(id);
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_clock_sdmmc_config_clock_host(pclock, id, val);
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if (is_enabled)
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_clock_sdmmc_set_enable(id);
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_clock_sdmmc_is_reset(id);
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}
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}
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void clock_sdmmc_get_card_clock_div(u32 *pclock, u16 *pdivisor, u32 type)
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{
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// Get Card clock divisor.
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switch (type)
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{
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case SDHCI_TIMING_MMC_ID: // Actual IO Freq: 380.59 KHz.
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*pclock = 26000;
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*pdivisor = 66;
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break;
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case SDHCI_TIMING_MMC_LS26:
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*pclock = 26000;
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*pdivisor = 1;
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break;
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case SDHCI_TIMING_MMC_HS52:
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*pclock = 52000;
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*pdivisor = 1;
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break;
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case SDHCI_TIMING_MMC_HS200:
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case SDHCI_TIMING_MMC_HS400:
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case SDHCI_TIMING_UHS_SDR104:
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*pclock = 200000;
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*pdivisor = 1;
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break;
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case SDHCI_TIMING_SD_ID: // Actual IO Freq: 380.43 KHz.
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*pclock = 25000;
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*pdivisor = 64;
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break;
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case SDHCI_TIMING_SD_DS12:
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case SDHCI_TIMING_UHS_SDR12:
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*pclock = 25000;
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*pdivisor = 1;
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break;
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case SDHCI_TIMING_SD_HS25:
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case SDHCI_TIMING_UHS_SDR25:
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*pclock = 50000;
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*pdivisor = 1;
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break;
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case SDHCI_TIMING_UHS_SDR50:
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*pclock = 100000;
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*pdivisor = 1;
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break;
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case SDHCI_TIMING_UHS_SDR82:
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*pclock = 164000;
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*pdivisor = 1;
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break;
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case SDHCI_TIMING_UHS_DDR50:
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*pclock = 40800;
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*pdivisor = 1;
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break;
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case SDHCI_TIMING_MMC_HS102: // Actual IO Freq: 99.84 MHz.
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*pclock = 200000;
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*pdivisor = 2;
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break;
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}
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}
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int clock_sdmmc_is_not_reset_and_enabled(u32 id)
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{
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return !_clock_sdmmc_is_reset(id) && _clock_sdmmc_is_enabled(id);
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}
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void clock_sdmmc_enable(u32 id, u32 val)
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{
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u32 clock = 0;
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if (_clock_sdmmc_is_enabled(id))
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_clock_sdmmc_clear_enable(id);
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_clock_sdmmc_set_reset(id);
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_clock_sdmmc_config_clock_host(&clock, id, val);
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_clock_sdmmc_set_enable(id);
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_clock_sdmmc_is_reset(id);
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usleep((100000 + clock - 1) / clock);
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_clock_sdmmc_clear_reset(id);
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_clock_sdmmc_is_reset(id);
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}
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void clock_sdmmc_disable(u32 id)
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{
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_clock_sdmmc_set_reset(id);
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_clock_sdmmc_clear_enable(id);
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_clock_sdmmc_is_reset(id);
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}
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