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https://github.com/Atmosphere-NX/Atmosphere.git
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70 lines
2.2 KiB
C
70 lines
2.2 KiB
C
/*
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* Copyright (c) 2018 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef EXOSPHERE_FLOW_CTLR_H
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#define EXOSPHERE_FLOW_CTLR_H
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#include <stdint.h>
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#include <stdbool.h>
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#include "cpu_context.h"
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#include "memory_map.h"
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/* Exosphere register definitions for the Tegra X1 Flow Controller. */
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static inline uintptr_t get_flow_base(void) {
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return MMIO_GET_DEVICE_ADDRESS(MMIO_DEVID_FLOWCTRL);
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}
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#define FLOW_BASE (get_flow_base())
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#define MAKE_FLOW_REG(ofs) MAKE_REG32(FLOW_BASE + ofs)
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#define FLOW_CTLR_HALT_COP_EVENTS_0 MAKE_FLOW_REG(0x004)
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#define FLOW_CTLR_FLOW_DBG_QUAL_0 MAKE_FLOW_REG(0x050)
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#define FLOW_CTLR_L2FLUSH_CONTROL_0 MAKE_FLOW_REG(0x094)
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#define FLOW_CTLR_BPMP_CLUSTER_CONTROL_0 MAKE_FLOW_REG(0x098)
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static const struct {
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unsigned int CPUN_CSR_OFS;
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unsigned int HALT_CPUN_EVENTS_OFS;
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unsigned int CC4_COREN_CTRL_OFS;
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} g_flow_core_offsets[NUM_CPU_CORES] = {
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{0x008, 0x000, 0x06C},
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{0x018, 0x014, 0x070},
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{0x020, 0x01C, 0x074},
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{0x028, 0x024, 0x078},
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};
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static inline void flow_set_cc4_ctrl(uint32_t core, uint32_t cc4_ctrl) {
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MAKE_FLOW_REG(g_flow_core_offsets[core].CC4_COREN_CTRL_OFS) = cc4_ctrl;
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}
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static inline void flow_set_halt_events(uint32_t core, bool halt_events) {
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MAKE_FLOW_REG(g_flow_core_offsets[core].HALT_CPUN_EVENTS_OFS) = (halt_events ? 0x40000F00 : 0x40000000);
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}
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static inline void flow_set_csr(uint32_t core, uint32_t csr) {
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MAKE_FLOW_REG(g_flow_core_offsets[core].CPUN_CSR_OFS) = (0x100 << core) | (csr << 12) | 0xC001;
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}
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static inline void flow_clear_csr0_and_events(uint32_t core) {
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MAKE_FLOW_REG(g_flow_core_offsets[core].CPUN_CSR_OFS) = 0;
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MAKE_FLOW_REG(g_flow_core_offsets[core].HALT_CPUN_EVENTS_OFS) = 0;
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}
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#endif
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