mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-12-23 10:52:13 +00:00
185 lines
6.7 KiB
C
185 lines
6.7 KiB
C
/*
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* Copyright (c) 2018 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __EXCEPTION_H__
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#define __EXCEPTION_H__
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/**
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* Borrowed fom Xen (not copyrightable as these are facts).
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* Description of the EL2 exception syndrome register.
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*/
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#define HSR_EC_UNKNOWN 0x00
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#define HSR_EC_WFI_WFE 0x01
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#define HSR_EC_CP15_32 0x03
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#define HSR_EC_CP15_64 0x04
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#define HSR_EC_CP14_32 0x05 /* Trapped MCR or MRC access to CP14 */
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#define HSR_EC_CP14_DBG 0x06 /* Trapped LDC/STC access to CP14 (only for debug registers) */
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#define HSR_EC_CP 0x07 /* HCPTR-trapped access to CP0-CP13 */
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#define HSR_EC_CP10 0x08
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#define HSR_EC_JAZELLE 0x09
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#define HSR_EC_BXJ 0x0a
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#define HSR_EC_CP14_64 0x0c
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#define HSR_EC_SVC32 0x11
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#define HSR_EC_HVC32 0x12
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#define HSR_EC_SMC32 0x13
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#define HSR_EC_HVC64 0x16
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#define HSR_EC_SMC64 0x17
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#define HSR_EC_SYSREG 0x18
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#define HSR_EC_INSTR_ABORT_LOWER_EL 0x20
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#define HSR_EC_INSTR_ABORT_CURR_EL 0x21
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#define HSR_EC_DATA_ABORT_LOWER_EL 0x24
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#define HSR_EC_DATA_ABORT_CURR_EL 0x25
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#define HSR_EC_BRK 0x3c
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/**
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* Borrowed fom Xen (not copyrightable as these are facts).
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* Description of the EL2 exception syndrome register.
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*/
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union esr {
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uint32_t bits;
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struct {
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unsigned long iss:25; /* Instruction Specific Syndrome */
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unsigned long len:1; /* Instruction length */
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unsigned long ec:6; /* Exception Class */
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};
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/* Common to all conditional exception classes (0x0N, except 0x00). */
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struct hsr_cond {
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unsigned long iss:20; /* Instruction Specific Syndrome */
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unsigned long cc:4; /* Condition Code */
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unsigned long ccvalid:1;/* CC Valid */
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unsigned long len:1; /* Instruction length */
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unsigned long ec:6; /* Exception Class */
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} cond;
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struct hsr_wfi_wfe {
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unsigned long ti:1; /* Trapped instruction */
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unsigned long sbzp:19;
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unsigned long cc:4; /* Condition Code */
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unsigned long ccvalid:1;/* CC Valid */
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unsigned long len:1; /* Instruction length */
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unsigned long ec:6; /* Exception Class */
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} wfi_wfe;
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/* reg, reg0, reg1 are 4 bits on AArch32, the fifth bit is sbzp. */
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struct hsr_cp32 {
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unsigned long read:1; /* Direction */
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unsigned long crm:4; /* CRm */
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unsigned long reg:5; /* Rt */
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unsigned long crn:4; /* CRn */
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unsigned long op1:3; /* Op1 */
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unsigned long op2:3; /* Op2 */
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unsigned long cc:4; /* Condition Code */
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unsigned long ccvalid:1;/* CC Valid */
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unsigned long len:1; /* Instruction length */
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unsigned long ec:6; /* Exception Class */
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} cp32; /* HSR_EC_CP15_32, CP14_32, CP10 */
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struct hsr_cp64 {
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unsigned long read:1; /* Direction */
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unsigned long crm:4; /* CRm */
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unsigned long reg1:5; /* Rt1 */
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unsigned long reg2:5; /* Rt2 */
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unsigned long sbzp2:1;
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unsigned long op1:4; /* Op1 */
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unsigned long cc:4; /* Condition Code */
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unsigned long ccvalid:1;/* CC Valid */
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unsigned long len:1; /* Instruction length */
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unsigned long ec:6; /* Exception Class */
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} cp64; /* HSR_EC_CP15_64, HSR_EC_CP14_64 */
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struct hsr_cp {
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unsigned long coproc:4; /* Number of coproc accessed */
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unsigned long sbz0p:1;
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unsigned long tas:1; /* Trapped Advanced SIMD */
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unsigned long res0:14;
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unsigned long cc:4; /* Condition Code */
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unsigned long ccvalid:1;/* CC Valid */
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unsigned long len:1; /* Instruction length */
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unsigned long ec:6; /* Exception Class */
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} cp; /* HSR_EC_CP */
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struct hsr_sysreg {
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unsigned long read:1; /* Direction */
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unsigned long crm:4; /* CRm */
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unsigned long reg:5; /* Rt */
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unsigned long crn:4; /* CRn */
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unsigned long op1:3; /* Op1 */
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unsigned long op2:3; /* Op2 */
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unsigned long op0:2; /* Op0 */
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unsigned long res0:3;
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unsigned long len:1; /* Instruction length */
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unsigned long ec:6;
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} sysreg; /* HSR_EC_SYSREG */
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struct hsr_iabt {
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unsigned long ifsc:6; /* Instruction fault status code */
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unsigned long res0:1;
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unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */
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unsigned long res1:1;
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unsigned long eat:1; /* External abort type */
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unsigned long res2:15;
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unsigned long len:1; /* Instruction length */
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unsigned long ec:6; /* Exception Class */
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} iabt; /* HSR_EC_INSTR_ABORT_* */
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struct hsr_dabt {
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unsigned long dfsc:6; /* Data Fault Status Code */
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unsigned long write:1; /* Write / not Read */
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unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */
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unsigned long cache:1; /* Cache Maintenance */
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unsigned long eat:1; /* External Abort Type */
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unsigned long sbzp0:4;
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unsigned long ar:1; /* Acquire Release */
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unsigned long sf:1; /* Sixty Four bit register */
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unsigned long reg:5; /* Register */
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unsigned long sign:1; /* Sign extend */
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unsigned long size:2; /* Access Size */
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unsigned long valid:1; /* Syndrome Valid */
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unsigned long len:1; /* Instruction length */
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unsigned long ec:6; /* Exception Class */
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} dabt; /* HSR_EC_DATA_ABORT_* */
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struct hsr_brk {
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unsigned long comment:16; /* Comment */
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unsigned long res0:9;
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unsigned long len:1; /* Instruction length */
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unsigned long ec:6; /* Exception Class */
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} brk;
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};
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/**
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* Structure that stores the saved register values on a hypercall.
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*/
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struct guest_state {
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uint64_t pc;
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uint64_t cpsr;
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uint64_t elr_el1;
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uint64_t spsr_el1;
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uint64_t sp_el0;
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uint64_t sp_el1;
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union esr esr_el2;
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uint64_t x[31];
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}
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__attribute__((packed));
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#endif
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