mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-12-23 10:52:13 +00:00
362 lines
12 KiB
C
362 lines
12 KiB
C
#include <stdint.h>
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#include <stddef.h>
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#include "utils.h"
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#include "cache.h"
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#include "se.h"
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void trigger_se_rsa_op(void *buf, size_t size);
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void trigger_se_blocking_op(unsigned int op, void *dst, size_t dst_size, const void *src, size_t src_size);
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/* Globals for driver. */
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volatile security_engine_t *g_security_engine;
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unsigned int (*g_se_callback)(void);
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unsigned int g_se_modulus_sizes[KEYSLOT_RSA_MAX];
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unsigned int g_se_exp_sizes[KEYSLOT_RSA_MAX];
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/* Initialize a SE linked list. */
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void ll_init(se_ll_t *ll, void *buffer, size_t size) {
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ll->num_entries = 0; /* 1 Entry. */
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if (buffer != NULL) {
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ll->addr_info.address = get_physical_address(buffer);
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ll->addr_info.size = (uint32_t) size;
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} else {
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ll->addr_info.address = 0;
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ll->addr_info.size = 0;
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}
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flush_dcache_range((uint8_t *)ll, (uint8_t *)ll + sizeof(*ll));
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}
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/* Set the global security engine pointer. */
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void set_security_engine_address(security_engine_t *security_engine) {
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g_security_engine = security_engine;
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}
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/* Get the global security engine pointer. */
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security_engine_t *get_security_engine_address(void) {
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return g_security_engine;
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}
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void set_security_engine_callback(unsigned int (*callback)(void)) {
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if (callback == NULL || g_se_callback != NULL) {
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panic();
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}
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g_se_callback = callback;
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}
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/* Fires on Security Engine operation completion. */
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void se_operation_completed(void) {
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if (g_security_engine == NULL) {
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panic();
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}
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g_security_engine->INT_ENABLE_REG = 0;
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if (g_se_callback != NULL) {
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g_se_callback();
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g_se_callback = NULL;
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}
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}
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/* Set the flags for an AES keyslot. */
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void set_aes_keyslot_flags(unsigned int keyslot, unsigned int flags) {
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if (g_security_engine == NULL || keyslot >= KEYSLOT_AES_MAX) {
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panic();
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}
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/* Misc flags. */
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if (flags & ~0x80) {
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g_security_engine->AES_KEYSLOT_FLAGS[keyslot] = ~flags;
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}
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/* Disable keyslot reads. */
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if (flags & 0x80) {
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g_security_engine->AES_KEY_READ_DISABLE_REG &= ~(1 << keyslot);
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}
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}
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/* Set the flags for an RSA keyslot. */
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void set_rsa_keyslot_flags(unsigned int keyslot, unsigned int flags) {
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if (g_security_engine == NULL || keyslot >= KEYSLOT_RSA_MAX) {
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panic();
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}
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/* Misc flags. */
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if (flags & ~0x80) {
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/* TODO: Why are flags assigned this way? */
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g_security_engine->RSA_KEYSLOT_FLAGS[keyslot] = (((flags >> 4) & 4) | (flags & 3)) ^ 7;
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}
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/* Disable keyslot reads. */
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if (flags & 0x80) {
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g_security_engine->RSA_KEY_READ_DISABLE_REG &= ~(1 << keyslot);
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}
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}
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void clear_aes_keyslot(unsigned int keyslot) {
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if (g_security_engine == NULL || keyslot >= KEYSLOT_AES_MAX) {
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panic();
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}
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/* Zero out the whole keyslot and IV. */
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for (unsigned int i = 0; i < 0x10; i++) {
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g_security_engine->AES_KEYTABLE_ADDR = (keyslot << 4) | i;
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g_security_engine->AES_KEYTABLE_DATA = 0;
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}
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}
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void clear_rsa_keyslot(unsigned int keyslot) {
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if (g_security_engine == NULL || keyslot >= KEYSLOT_RSA_MAX) {
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panic();
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}
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/* Zero out the whole keyslot. */
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for (unsigned int i = 0; i < 0x40; i++) {
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/* Select Keyslot Modulus[i] */
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g_security_engine->RSA_KEYTABLE_ADDR = (keyslot << 7) | i | 0x40;
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g_security_engine->RSA_KEYTABLE_DATA = 0;
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}
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for (unsigned int i = 0; i < 0x40; i++) {
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/* Select Keyslot Expontent[i] */
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g_security_engine->RSA_KEYTABLE_ADDR = (keyslot << 7) | i;
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g_security_engine->RSA_KEYTABLE_DATA = 0;
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}
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}
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void set_aes_keyslot(unsigned int keyslot, const void *key, size_t key_size) {
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if (g_security_engine == NULL || keyslot >= KEYSLOT_AES_MAX || key_size > KEYSIZE_AES_MAX) {
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panic();
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}
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for (size_t i = 0; i < (key_size >> 2); i++) {
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g_security_engine->AES_KEYTABLE_ADDR = (keyslot << 4) | i;
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g_security_engine->AES_KEYTABLE_DATA = read32le(key, 4 * i);
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}
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}
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void set_rsa_keyslot(unsigned int keyslot, const void *modulus, size_t modulus_size, const void *exponent, size_t exp_size) {
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if (g_security_engine == NULL || keyslot >= KEYSLOT_RSA_MAX || modulus_size > KEYSIZE_RSA_MAX || exp_size > KEYSIZE_RSA_MAX) {
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panic();
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}
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for (size_t i = 0; i < (modulus_size >> 2); i++) {
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g_security_engine->RSA_KEYTABLE_ADDR = (keyslot << 7) | 0x40 | i;
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g_security_engine->RSA_KEYTABLE_DATA = read32be(modulus, 4 * i);
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}
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for (size_t i = 0; i < (exp_size >> 2); i++) {
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g_security_engine->RSA_KEYTABLE_ADDR = (keyslot << 7) | i;
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g_security_engine->RSA_KEYTABLE_DATA = read32be(exponent, 4 * i);
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}
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g_se_modulus_sizes[keyslot] = modulus_size;
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g_se_exp_sizes[keyslot] = exp_size;
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}
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void set_aes_keyslot_iv(unsigned int keyslot, const void *iv, size_t iv_size) {
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if (g_security_engine == NULL || keyslot >= KEYSLOT_AES_MAX || iv_size > 0x10) {
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panic();
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}
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for (size_t i = 0; i < (iv_size >> 2); i++) {
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g_security_engine->AES_KEYTABLE_ADDR = (keyslot << 4) | 8 | i;
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g_security_engine->AES_KEYTABLE_DATA = read32le(iv, 4 * i);
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}
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}
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void set_se_ctr(const void *ctr) {
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if (g_security_engine == NULL) {
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panic();
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}
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for (unsigned int i = 0; i < 4; i++) {
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g_security_engine->CRYPTO_CTR_REG[i] = read32le(ctr, i * 4);
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}
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}
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void decrypt_data_into_keyslot(unsigned int keyslot_dst, unsigned int keyslot_src, const void *wrapped_key, size_t wrapped_key_size) {
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if (g_security_engine == NULL || keyslot_dst >= KEYSLOT_AES_MAX || keyslot_src >= KEYSIZE_AES_MAX || wrapped_key_size > KEYSIZE_AES_MAX) {
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panic();
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}
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g_security_engine->CONFIG_REG = (ALG_AES_DEC | DST_KEYTAB);
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g_security_engine->CRYPTO_REG = keyslot_src << 24;
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g_security_engine->BLOCK_COUNT_REG = 0;
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g_security_engine->CRYPTO_KEYTABLE_DST_REG = keyslot_dst << 8;
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flush_dcache_range(wrapped_key, (const uint8_t *)wrapped_key + wrapped_key_size);
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trigger_se_aes_op(OP_START, NULL, 0, wrapped_key, wrapped_key_size);
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}
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void se_aes_crypt_insecure_internal(unsigned int keyslot, uint32_t out_ll_paddr, uint32_t in_ll_paddr, size_t size, unsigned int crypt_config, int encrypt, unsigned int (*callback)(void)) {
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if (g_security_engine == NULL || keyslot >= KEYSLOT_AES_MAX) {
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panic();
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}
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if (size == 0) {
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return;
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}
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/* Setup Config register. */
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encrypt &= 1;
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if (encrypt) {
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g_security_engine->CONFIG_REG = (ALG_AES_ENC | DST_MEMORY);
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} else {
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g_security_engine->CONFIG_REG = (ALG_AES_DEC | DST_MEMORY);
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}
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/* Setup Crypto register. */
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g_security_engine->CRYPTO_REG = crypt_config | (keyslot << 24) | (encrypt << 8);
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/* Mark this encryption as insecure -- this makes the SE not a secure busmaster. */
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g_security_engine->CRYPTO_REG |= 0x80000000;
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/* Appropriate number of blocks. */
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g_security_engine->BLOCK_COUNT_REG = (size >> 4) - 1;
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/* Set the callback, for after the async operation. */
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set_security_engine_callback(callback);
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/* Enable SE Interrupt firing for async op. */
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g_security_engine->INT_ENABLE_REG = 0x10;
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/* Setup Input/Output lists */
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g_security_engine->IN_LL_ADDR_REG = in_ll_paddr;
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g_security_engine->OUT_LL_ADDR_REG = out_ll_paddr;
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/* Set registers for operation. */
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g_security_engine->ERR_STATUS_REG = g_security_engine->ERR_STATUS_REG;
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g_security_engine->INT_STATUS_REG = g_security_engine->INT_STATUS_REG;
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g_security_engine->OPERATION_REG = 1;
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/* Ensure writes go through. */
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__asm__ __volatile__ ("dsb ish" : : : "memory");
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}
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void se_aes_ctr_crypt_insecure(unsigned int keyslot, uint32_t out_ll_paddr, uint32_t in_ll_paddr, size_t size, const void *ctr, unsigned int (*callback)(void)) {
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if (g_security_engine == NULL) {
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panic();
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}
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/* Unknown what this write does, but official code writes it for CTR mode. */
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g_security_engine->_0x80C = 1;
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set_se_ctr(ctr);
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se_aes_crypt_insecure_internal(keyslot, out_ll_paddr, in_ll_paddr, size, 0x81E, 1, callback);
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}
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void se_aes_cbc_encrypt_insecure(unsigned int keyslot, uint32_t out_ll_paddr, uint32_t in_ll_paddr, size_t size, const void *iv, unsigned int (*callback)(void)) {
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if (g_security_engine == NULL) {
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panic();
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}
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set_aes_keyslot_iv(keyslot, iv, 0x10);
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se_aes_crypt_insecure_internal(keyslot, out_ll_paddr, in_ll_paddr, size, 0x44, 1, callback);
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}
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void se_aes_cbc_decrypt_insecure(unsigned int keyslot, uint32_t out_ll_paddr, uint32_t in_ll_paddr, size_t size, const void *iv, unsigned int (*callback)(void)) {
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if (g_security_engine == NULL) {
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panic();
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}
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set_aes_keyslot_iv(keyslot, iv, 0x10);
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se_aes_crypt_insecure_internal(keyslot, out_ll_paddr, in_ll_paddr, size, 0x66, 0, callback);
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}
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void se_exp_mod(unsigned int keyslot, void *buf, size_t size, unsigned int (*callback)(void)) {
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uint8_t stack_buf[KEYSIZE_RSA_MAX];
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if (g_security_engine == NULL || keyslot >= KEYSLOT_RSA_MAX || size > KEYSIZE_RSA_MAX) {
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panic();
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}
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/* Endian swap the input. */
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for (size_t i = size; i > 0; i--) {
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stack_buf[i] = *((uint8_t *)buf + size - i);
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}
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g_security_engine->CONFIG_REG = (ALG_RSA | DST_RSAREG);
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g_security_engine->RSA_CONFIG = keyslot << 24;
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g_security_engine->RSA_KEY_SIZE_REG = (g_se_modulus_sizes[keyslot] >> 6) - 1;
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g_security_engine->RSA_EXP_SIZE_REG = g_se_exp_sizes[keyslot] >> 2;
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set_security_engine_callback(callback);
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/* Enable SE Interrupt firing for async op. */
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g_security_engine->INT_ENABLE_REG = 0x10;
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flush_dcache_range(stack_buf, stack_buf + KEYSIZE_RSA_MAX);
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trigger_se_rsa_op(stack_buf, size);
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while (!(g_security_engine->INT_STATUS_REG & 2)) { /* Wait a while */ }
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}
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void se_get_exp_mod_output(void *buf, size_t size) {
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size_t num_dwords = (size >> 2);
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if (num_dwords < 1) {
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return;
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}
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uint32_t *p_out = ((uint32_t *)buf) + num_dwords - 1;
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uint32_t out_ofs = 0;
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/* Copy endian swapped output. */
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while (num_dwords) {
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*p_out = read32be(g_security_engine->RSA_OUTPUT, offset);
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offset += 4;
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p_out--;
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num_dwords--;
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}
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}
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void trigger_se_rsa_op(void *buf, size_t size) {
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se_ll_t in_ll;
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ll_init(&in_ll, buf, size);
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/* Set the input LL. */
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g_security_engine->IN_LL_ADDR_REG = get_physical_address(&in_ll);
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/* Set registers for operation. */
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g_security_engine->ERR_STATUS_REG = g_security_engine->ERR_STATUS_REG;
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g_security_engine->INT_STATUS_REG = g_security_engine->INT_STATUS_REG;
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g_security_engine->OPERATION_REG = 1;
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/* Ensure writes go through. */
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__asm__ __volatile__ ("dsb ish" : : : "memory");
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}
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void trigger_se_blocking_op(unsigned int op, void *dst, size_t dst_size, const void *src, size_t src_size) {
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se_ll_t in_ll;
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se_ll_t out_ll;
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ll_init(&in_ll, src, src_size);
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ll_init(&out_ll, dst, dst_size);
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/* Set the LLs. */
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g_security_engine->IN_LL_ADDR_REG = get_physical_address(&in_ll);
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g_security_enging->OUT_LL_ADDR_REG = get_physical_address(&out_ll);
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/* Set registers for operation. */
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g_security_engine->ERR_STATUS_REG = g_security_engine->ERR_STATUS_REG;
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g_security_engine->INT_STATUS_REG = g_security_engine->INT_STATUS_REG;
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g_security_engine->OPERATION_REG = op;
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while (!(g_security_engine->INT_STATUS_REG & 0x10)) { /* Wait a while */ }
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se_check_for_error();
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}
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void se_check_for_error(void) {
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if (g_security_engine == NULL) {
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panic();
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}
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if (g_security_engine->INT_STATUS_REG & 0x10000 || g_security_engine->FLAGS_REG & 3 || g_security_engine->ERR_STATUS_REG) {
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panic();
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}
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}
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