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74 lines
2.5 KiB
C
74 lines
2.5 KiB
C
/*
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* Copyright (c) 2018-2019 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "utils.h"
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#include "sc7.h"
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#include "emc.h"
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#include "pmc.h"
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#include "timer.h"
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static void emc_trigger_timing_update(void) {
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EMC_TIMING_CONTROL_0 = 1;
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while (EMC_EMC_STATUS_0 & 0x800000) {
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/* Wait until TIMING_UPDATE_STALLED is unset. */
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}
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}
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/* Puts DRAM into self refresh mode. */
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void emc_put_dram_in_self_refresh_mode(void) {
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/* Verify CH1_ENABLE [PMC]. */
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if (!(EMC_FBIO_CFG7_0 & 4)) {
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reboot();
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}
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/* Clear config. */
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EMC_CFG_0 = 0;
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emc_trigger_timing_update();
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timer_wait(5);
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/* Set calibration intervals. */
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EMC_ZCAL_INTERVAL_0 = 0;
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EMC_AUTO_CAL_CONFIG_0 = 0x600; /* AUTO_CAL_MEASURE_STALL | AUTO_CAL_UPDATE_STALL */
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/* If EMC0 mirror is set, clear digital DLL. */
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if (EMC0_CFG_DIG_DLL_0 & 1) {
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EMC_CFG_DIG_DLL_0 &= 0xFFFFFFFE;
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emc_trigger_timing_update();
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while (EMC0_CFG_DIG_DLL_0 & 1) { /* Wait for EMC0 to clear. */ }
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while (EMC1_CFG_DIG_DLL_0 & 1) { /* Wait for EMC1 to clear. */ }
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} else {
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emc_trigger_timing_update();
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}
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/* Stall all transactions to DRAM. */
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EMC_REQ_CTRL_0 = 3; /* STALL_ALL_WRITES | STALL_ALL_READS. */
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while (!(EMC0_EMC_STATUS_0 & 4)) { /* Wait for NO_OUTSTANDING_TRANSACTIONS for EMC0. */ }
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while (!(EMC1_EMC_STATUS_0 & 4)) { /* Wait for NO_OUTSTANDING_TRANSACTIONS for EMC1. */ }
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/* Enable Self-Refresh Mode. */
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EMC_SELF_REF_0 |= 1;
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/* Wait until we see the right devices in self refresh mode. */
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uint32_t num_populated_devices = 1;
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if (EMC_ADR_CFG_0) {
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num_populated_devices = 3;
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}
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while (((EMC0_EMC_STATUS_0 >> 8) & 3) != num_populated_devices) { /* Wait for EMC0 DRAM_IN_SELF_REFRESH to be correct. */ }
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while (((EMC1_EMC_STATUS_0 >> 8) & 3) != num_populated_devices) { /* Wait for EMC1 DRAM_IN_SELF_REFRESH to be correct. */ }
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}
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