mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-11-23 20:32:10 +00:00
286 lines
No EOL
13 KiB
C++
286 lines
No EOL
13 KiB
C++
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <exosphere.hpp>
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#include "secmon_setup.hpp"
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namespace ams::secmon {
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namespace setup {
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#include "secmon_cache_impl.inc"
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}
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namespace {
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constexpr inline uintptr_t MC = MemoryRegionPhysicalDeviceMemoryController.GetAddress();
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using namespace ams::mmu;
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constexpr inline PageTableMappingAttribute MappingAttributesEl3SecureRwCode = AddMappingAttributeIndex(PageTableMappingAttributes_El3SecureRwCode, MemoryAttributeIndexNormal);
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void SetupCpuCommonControllers() {
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/* Set cpuactlr_el1. */
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{
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util::BitPack64 cpuactlr = {};
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cpuactlr.Set<hw::CpuactlrEl1CortexA57::NonCacheableStreamingEnhancement>(1);
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cpuactlr.Set<hw::CpuactlrEl1CortexA57::DisableLoadPassDmb>(1);
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HW_CPU_SET_CPUACTLR_EL1(cpuactlr);
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}
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/* Set cpuectlr_el1. */
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{
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util::BitPack64 cpuectlr = {};
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cpuectlr.Set<hw::CpuectlrEl1CortexA57::Smpen>(1);
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cpuectlr.Set<hw::CpuectlrEl1CortexA57::L2LoadStoreDataPrefetchDistance>(3);
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cpuectlr.Set<hw::CpuectlrEl1CortexA57::L2InstructionFetchPrefetchDistance>(3);
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HW_CPU_SET_CPUECTLR_EL1(cpuectlr);
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}
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/* Prevent instruction reordering. */
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hw::InstructionSynchronizationBarrier();
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}
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void SetupCpuEl3Controllers() {
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/* Set scr_el3. */
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{
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util::BitPack32 scr = {};
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scr.Set<hw::ScrEl3::Ns >(1); /* Set EL0/EL1 as Non-Secure. */
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scr.Set<hw::ScrEl3::Irq >(0); /* IRQs are taken in IRQ mode. */
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scr.Set<hw::ScrEl3::Fiq >(1); /* FIQs are taken in Monitor mode. */
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scr.Set<hw::ScrEl3::Ea >(1); /* External aborts are taken in Monitor mode. */
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scr.Set<hw::ScrEl3::Fw >(1); /* CPSR.F is non-secure writable. */
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scr.Set<hw::ScrEl3::Aw >(1); /* CPSR.A is non-secure writable. */
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scr.Set<hw::ScrEl3::Net >(0); /* This bit is not implemented. */
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scr.Set<hw::ScrEl3::Smd >(0); /* Secure Monitor Call is allowed. */
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scr.Set<hw::ScrEl3::Hce >(0); /* Hypervisor Calls are disabled. */ /* TODO: Enable for thermosphere? */
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scr.Set<hw::ScrEl3::Sif >(1); /* Secure mode cannot fetch instructions from non-secure memory. */
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scr.Set<hw::ScrEl3::RwCortexA53>(1); /* Reserved bit. N probably sets it because on Cortex A53, this sets kernel as aarch64. */
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scr.Set<hw::ScrEl3::StCortexA53>(0); /* Reserved bit. On Cortex A53, this sets secure registers to EL3 only. */
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scr.Set<hw::ScrEl3::Twi >(0); /* WFI is not trapped. */
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scr.Set<hw::ScrEl3::Twe >(0); /* WFE is not trapped. */
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HW_CPU_SET_SCR_EL3(scr);
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}
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/* Set ttbr0_el3. */
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{
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constexpr u64 ttbr0 = MemoryRegionPhysicalTzramL1PageTable.GetAddress();
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HW_CPU_SET_TTBR0_EL3(ttbr0);
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}
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/* Set tcr_el3. */
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{
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util::BitPack32 tcr = { hw::TcrEl3::Res1 };
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tcr.Set<hw::TcrEl3::T0sz >(31); /* Configure TTBR0 addressed size to be 64 GiB */
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tcr.Set<hw::TcrEl3::Irgn0>(1); /* Configure PTE walks as inner write-back write-allocate cacheable */
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tcr.Set<hw::TcrEl3::Orgn0>(1); /* Configure PTE walks as outer write-back write-allocate cacheable */
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tcr.Set<hw::TcrEl3::Sh0 >(3); /* Configure PTE walks as inner shareable */
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tcr.Set<hw::TcrEl3::Tg0 >(0); /* Set TTBR0_EL3 granule as 4 KiB */
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tcr.Set<hw::TcrEl3::Ps >(1); /* Set the physical addrss size as 36-bit (64 GiB) */
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tcr.Set<hw::TcrEl3::Tbi >(0); /* Top byte is not ignored in addrss calculations */
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HW_CPU_SET_TCR_EL3(tcr);
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}
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/* Clear cptr_el3. */
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{
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util::BitPack32 cptr = {};
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cptr.Set<hw::CptrEl3::Tfp >(0); /* FP/SIMD instructions don't trap. */
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cptr.Set<hw::CptrEl3::Tta >(0); /* Reserved bit (no trace functionality present). */
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cptr.Set<hw::CptrEl3::Tcpac>(0); /* Access to cpacr_El1 does not trap. */
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HW_CPU_SET_CPTR_EL3(cptr);
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}
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/* Set mair_el3. */
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{
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u64 mair = (MemoryRegionAttributes_Normal << (MemoryRegionAttributeWidth * MemoryAttributeIndexNormal)) |
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(MemoryRegionAttributes_Device << (MemoryRegionAttributeWidth * MemoryAttributeIndexDevice));
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HW_CPU_SET_MAIR_EL3(mair);
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}
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/* Set vectors. */
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{
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constexpr u64 vectors = MemoryRegionVirtualTzramProgramExceptionVectors.GetAddress();
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HW_CPU_SET_VBAR_EL3(vectors);
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}
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/* Prevent instruction re-ordering around this point. */
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hw::InstructionSynchronizationBarrier();
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}
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void EnableMmu() {
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/* Create sctlr value. */
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util::BitPack64 sctlr = { hw::SctlrEl3::Res1 };
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sctlr.Set<hw::SctlrEl3::M>(1); /* Globally enable the MMU. */
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sctlr.Set<hw::SctlrEl3::A>(0); /* Disable alignment fault checking. */
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sctlr.Set<hw::SctlrEl3::C>(1); /* Globally enable the data and unified caches. */
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sctlr.Set<hw::SctlrEl3::Sa>(0); /* Disable stack alignment checking. */
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sctlr.Set<hw::SctlrEl3::I>(1); /* Globally enable the instruction cache. */
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sctlr.Set<hw::SctlrEl3::Wxn>(0); /* Do not force writable pages to be ExecuteNever. */
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sctlr.Set<hw::SctlrEl3::Ee>(0); /* Exceptions should be little endian. */
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/* Ensure all writes are done before turning on the mmu. */
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hw::DataSynchronizationBarrierInnerShareable();
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/* Invalidate the entire tlb. */
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hw::InvalidateEntireTlb();
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/* Ensure instruction consistency. */
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hw::DataSynchronizationBarrierInnerShareable();
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hw::InstructionSynchronizationBarrier();
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/* Set sctlr_el3. */
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HW_CPU_SET_SCTLR_EL3(sctlr);
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hw::InstructionSynchronizationBarrier();
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}
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bool IsExitLp0() {
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return reg::Read(MC + MC_SECURITY_CFG3) == 0;
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}
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constexpr void AddPhysicalTzramIdentityMappingImpl(u64 *l1, u64 *l2, u64 *l3) {
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/* Define extents. */
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const uintptr_t start_address = MemoryRegionPhysicalTzram.GetAddress();
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const size_t size = MemoryRegionPhysicalTzram.GetSize();
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const uintptr_t end_address = start_address + size;
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/* Flush cache for the L3 page table entries. */
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{
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const uintptr_t start = GetL3EntryIndex(start_address);
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const uintptr_t end = GetL3EntryIndex(end_address);
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for (uintptr_t i = start; i < end; i += hw::DataCacheLineSize / sizeof(*l3)) {
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if (!std::is_constant_evaluated()) { hw::FlushDataCacheLine(l3 + i); }
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}
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}
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/* Flush cache for the L2 page table entry. */
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if (!std::is_constant_evaluated()) { hw::FlushDataCacheLine(l2 + GetL2EntryIndex(start_address)); }
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/* Flush cache for the L1 page table entry. */
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if (!std::is_constant_evaluated()) { hw::FlushDataCacheLine(l1 + GetL1EntryIndex(start_address)); }
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/* Add the L3 mappings. */
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SetL3BlockEntry(l3, start_address, start_address, size, MappingAttributesEl3SecureRwCode);
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/* Add the L2 entry for the physical tzram region. */
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SetL2TableEntry(l2, MemoryRegionPhysicalTzramL2.GetAddress(), MemoryRegionPhysicalTzramL2L3PageTable.GetAddress(), PageTableTableAttributes_El3SecureCode);
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/* Add the L1 entry for the physical region. */
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SetL1TableEntry(l1, MemoryRegionPhysical.GetAddress(), MemoryRegionPhysicalTzramL2L3PageTable.GetAddress(), PageTableTableAttributes_El3SecureCode);
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static_assert(GetL1EntryIndex(MemoryRegionPhysical.GetAddress()) == 1);
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/* Invalidate the data cache for the L3 page table entries. */
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{
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const uintptr_t start = GetL3EntryIndex(start_address);
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const uintptr_t end = GetL3EntryIndex(end_address);
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for (uintptr_t i = start; i < end; i += hw::DataCacheLineSize / sizeof(*l3)) {
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if (!std::is_constant_evaluated()) { hw::InvalidateDataCacheLine(l3 + i); }
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}
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}
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/* Flush cache for the L2 page table entry. */
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if (!std::is_constant_evaluated()) { hw::InvalidateDataCacheLine(l2 + GetL2EntryIndex(start_address)); }
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/* Flush cache for the L1 page table entry. */
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if (!std::is_constant_evaluated()) { hw::InvalidateDataCacheLine(l1 + GetL1EntryIndex(start_address)); }
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}
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void AddPhysicalTzramIdentityMapping() {
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/* Get page table extents. */
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u64 * const l1 = MemoryRegionPhysicalTzramL1PageTable.GetPointer<u64>();
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u64 * const l2_l3 = MemoryRegionPhysicalTzramL2L3PageTable.GetPointer<u64>();
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/* Add the mapping. */
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AddPhysicalTzramIdentityMappingImpl(l1, l2_l3, l2_l3);
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/* Ensure that mappings are consistent. */
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setup::EnsureMappingConsistency();
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}
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}
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void SetupCpuMemoryControllersEnableMmu() {
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SetupCpuCommonControllers();
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SetupCpuEl3Controllers();
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EnableMmu();
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}
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void SetupSocDmaControllers() {
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/* Ensure that our caches are managed. */
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setup::InvalidateEntireDataCache();
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setup::EnsureInstructionConsistency();
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/* Lock tsec. */
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tsec::Lock();
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/* Enable SWID[0] for all bits. */
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reg::Write(AHB_ARBC(AHB_MASTER_SWID), ~0u);
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/* Clear SWID1 for all bits. */
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reg::Write(AHB_ARBC(AHB_MASTER_SWID_1), 0u);
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/* Set MSELECT config to set WRAP_TO_INCR_SLAVE0(APC) | WRAP_TO_INCR_SLAVE1(PCIe) | WRAP_TO_INCR_SLAVE2(GPU) */
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/* and clear ERR_RESP_EN_SLAVE1(PCIe) | ERR_RESP_EN_SLAVE2(GPU) */
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{
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auto mselect_cfg = reg::Read(MSELECT(MSELECT_CONFIG));
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mselect_cfg &= ~(1u << 24); /* Clear ERR_RESP_EN_SLAVE1(PCIe) */
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mselect_cfg &= ~(1u << 25); /* Clear ERR_RESP_EN_SLAVE2(GPU) */
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mselect_cfg |= (1u << 27); /* Set WRAP_TO_INCR_SLAVE0(APC) */
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mselect_cfg |= (1u << 28); /* Set WRAP_TO_INCR_SLAVE1(PCIe) */
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mselect_cfg |= (1u << 29); /* Set WRAP_TO_INCR_SLAVE2(GPU) */
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reg::Write(MSELECT(MSELECT_CONFIG), mselect_cfg);
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}
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/* Disable USB, USB2, AHB-DMA from arbitration. */
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{
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auto arb_dis = reg::Read(AHB_ARBC(AHB_ARBITRATION_DISABLE));
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arb_dis |= (1u << 5); /* Disable AHB-DMA */
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arb_dis |= (1u << 6); /* Disable USB */
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arb_dis |= (1u << 18); /* Disable USB2 */
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reg::Write(AHB_ARBC(AHB_ARBITRATION_DISABLE), arb_dis);
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}
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/* Select high priority group with priority 7. */
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{
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u32 priority_ctrl = {};
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priority_ctrl |= (7u << 29); /* Set group 7. */
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priority_ctrl |= (1u << 0); /* Set high priority. */
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reg::Write(AHB_ARBC(AHB_ARBITRATION_PRIORITY_CTRL), priority_ctrl);
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}
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/* Prevent splitting AHB writes to TZRAM. */
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{
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reg::Write(AHB_ARBC(AHB_GIZMO_TZRAM), (1u << 7));
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}
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}
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void SetupSocDmaControllersCpuMemoryControllersEnableMmuWarmboot() {
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/* If this is being called from lp0 exit, we want to setup the soc dma controllers. */
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if (IsExitLp0()) {
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SetupSocDmaControllers();
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}
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/* Add a physical TZRAM identity map. */
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AddPhysicalTzramIdentityMapping();
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/* Initialize cpu memory controllers and the MMU. */
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SetupCpuMemoryControllersEnableMmu();
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}
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} |