mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-11-05 19:51:45 +00:00
480 lines
15 KiB
C
480 lines
15 KiB
C
#include <stdint.h>
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#include "utils.h"
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#include "configitem.h"
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#include "cpu_context.h"
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#include "smc_api.h"
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#include "smc_user.h"
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#include "se.h"
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#include "userpage.h"
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#include "titlekey.h"
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#define SMC_USER_HANDLERS 0x13
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#define SMC_PRIV_HANDLERS 0x9
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/* User SMC prototypes */
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uint32_t smc_set_config(smc_args_t *args);
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uint32_t smc_get_config(smc_args_t *args);
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uint32_t smc_check_status(smc_args_t *args);
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uint32_t smc_get_result(smc_args_t *args);
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uint32_t smc_exp_mod(smc_args_t *args);
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uint32_t smc_get_random_bytes_for_user(smc_args_t *args);
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uint32_t smc_generate_aes_kek(smc_args_t *args);
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uint32_t smc_load_aes_key(smc_args_t *args);
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uint32_t smc_crypt_aes(smc_args_t *args);
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uint32_t smc_generate_specific_aes_key(smc_args_t *args);
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uint32_t smc_compute_cmac(smc_args_t *args);
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uint32_t smc_load_rsa_oaep_key(smc_args_t *args);
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uint32_t smc_decrypt_rsa_private_key(smc_args_t *args);
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uint32_t smc_load_secure_exp_mod_key(smc_args_t *args);
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uint32_t smc_secure_exp_mod(smc_args_t *args);
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uint32_t smc_unwrap_rsa_oaep_wrapped_titlekey(smc_args_t *args);
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uint32_t smc_load_titlekey(smc_args_t *args);
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uint32_t smc_unwrap_aes_wrapped_titlekey(smc_args_t *args);
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/* Privileged SMC prototypes */
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uint32_t smc_cpu_suspend(smc_args_t *args);
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uint32_t smc_cpu_off(smc_args_t *args);
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uint32_t smc_cpu_on(smc_args_t *args);
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/* uint32_t smc_get_config(smc_args_t *args); */
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uint32_t smc_get_random_bytes_for_priv(smc_args_t *args);
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uint32_t smc_panic(smc_args_t *args);
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uint32_t smc_configure_carveout(smc_args_t *args);
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uint32_t smc_read_write_register(smc_args_t *args);
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typedef struct {
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uint32_t id;
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uint32_t (*handler)(smc_args_t *args);
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} smc_table_entry_t;
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typedef struct {
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smc_table_entry_t *handlers;
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uint32_t num_handlers;
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} smc_table_t;
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smc_table_entry_t g_smc_user_table[SMC_USER_HANDLERS] = {
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{0, NULL},
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{0xC3000401, smc_set_config},
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{0xC3000002, smc_get_config},
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{0xC3000003, smc_check_status},
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{0xC3000404, smc_get_result},
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{0xC3000E05, smc_exp_mod},
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{0xC3000006, smc_get_random_bytes_for_user},
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{0xC3000007, smc_generate_aes_kek},
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{0xC3000008, smc_load_aes_key},
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{0xC3000009, smc_crypt_aes},
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{0xC300000A, smc_generate_specific_aes_key},
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{0xC300040B, smc_compute_cmac},
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{0xC300100C, smc_load_rsa_oaep_key},
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{0xC300100D, smc_decrypt_rsa_private_key},
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{0xC300100E, smc_load_secure_exp_mod_key},
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{0xC300060F, smc_secure_exp_mod},
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{0xC3000610, smc_unwrap_rsa_oaep_wrapped_titlekey},
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{0xC3000011, smc_load_titlekey},
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{0xC3000012, smc_unwrap_aes_wrapped_titlekey}
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};
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smc_table_entry_t g_smc_priv_table[SMC_PRIV_HANDLERS] = {
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{0, NULL},
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{0xC4000001, smc_cpu_suspend},
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{0x84000002, smc_cpu_off},
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{0xC4000003, smc_cpu_on},
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{0xC3000004, smc_get_config}, /* NOTE: Same function as for USER */
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{0xC3000005, smc_get_random_bytes_for_priv},
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{0xC3000006, smc_panic},
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{0xC3000007, smc_configure_carveout},
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{0xC3000008, smc_read_write_register}
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};
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smc_table_t g_smc_tables[2] = {
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{ /* SMC_HANDLER_USER */
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g_smc_user_table,
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SMC_USER_HANDLERS
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},
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{ /* SMC_HANDLER_PRIV */
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g_smc_priv_table,
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SMC_PRIV_HANDLERS
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}
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};
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bool g_is_smc_in_progress = false;
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uint32_t (*g_smc_callback)(void *, uint64_t) = NULL;
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uint64_t g_smc_callback_key = 0;
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uint64_t try_set_smc_callback(uint32_t (*callback)(void *, uint64_t)) {
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uint64_t key;
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/* TODO: Atomics... */
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if (g_smc_callback_key) {
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return 0;
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}
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se_generate_random(KEYSLOT_SWITCH_RNGKEY, &key, sizeof(uint64_t));
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g_smc_callback_key = key;
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g_smc_callback = callback;
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return key;
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}
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void clear_smc_callback(uint64_t key) {
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/* TODO: Atomics... */
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if (g_smc_callback_key == key) {
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g_smc_callback_key = 0;
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}
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}
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void call_smc_handler(uint32_t handler_id, smc_args_t *args) {
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unsigned char smc_id;
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unsigned int result;
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unsigned int (*smc_handler)(smc_args_t *args);
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/* Validate top-level handler. */
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if (handler_id != SMC_HANDLER_USER && handler_id != SMC_HANDLER_PRIV) {
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panic();
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}
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/* Validate core is appropriate for handler. */
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if (handler_id == SMC_HANDLER_USER && get_core_id() != 3) {
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/* USER SMCs must be called via svcCallSecureMonitor on core 3 (where spl runs) */
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panic();
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}
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/* Validate sub-handler index */
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if ((smc_id = (unsigned char)args->X[0]) >= g_smc_tables[handler_id].num_handlers) {
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panic();
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}
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/* Validate sub-handler */
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if (g_smc_tables[handler_id].handlers[smc_id].id != args->X[0]) {
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panic();
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}
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/* Validate handler. */
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if ((smc_handler = g_smc_tables[handler_id].handlers[smc_id].handler) == NULL) {
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panic();
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}
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/* Call function. */
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args->X[0] = smc_handler(args);
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}
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uint32_t smc_wrapper_sync(smc_args_t *args, uint32_t (*handler)(smc_args_t *)) {
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uint32_t result;
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/* TODO: Make g_is_smc_in_progress atomic. */
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if (g_is_smc_in_progress) {
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return 3;
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}
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g_is_smc_in_progress = true;
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result = handler(args);
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g_is_smc_in_progress = false;
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return result;
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}
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uint32_t smc_wrapper_async(smc_args_t *args, uint32_t (*handler)(smc_args_t *), uint32_t (*callback)(void *, uint64_t)) {
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uint32_t result;
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uint64_t key;
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/* TODO: Make g_is_smc_in_progress atomic. */
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if (g_is_smc_in_progress) {
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return 3;
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}
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g_is_smc_in_progress = 1;
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if ((key = try_set_smc_callback(callback)) != 0) {
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result = handler(args);
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if (result == 0) {
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/* Pass the status check key back to userland. */
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args->X[1] = key;
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/* Early return, leaving g_is_smc_in_progress == 1 */
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return result;
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} else {
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/* No status to check. */
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clear_smc_callback(key);
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}
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} else {
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/* smcCheckStatus needs to be called. */
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result = 3;
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}
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g_is_smc_in_progress = false;
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return result;
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}
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uint32_t smc_set_config(smc_args_t *args) {
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/* Actual value presumed in X3 on hardware. */
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return configitem_set((enum ConfigItem)args->X[1], args->X[3]);
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}
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uint32_t smc_get_config(smc_args_t *args) {
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uint64_t out_item = 0;
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uint32_t result;
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result = configitem_get((enum ConfigItem)args->X[1], &out_item);
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args->X[1] = out_item;
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return result;
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}
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uint32_t smc_check_status(smc_args_t *args) {
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if (g_smc_callback_key == 0) {
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return 4;
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}
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if (args->X[1] != g_smc_callback_key) {
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return 5;
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}
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args->X[1] = g_smc_callback(NULL, 0);
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g_smc_callback_key = 0;
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return 0;
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}
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uint32_t smc_get_result(smc_args_t *) {
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uint32_t status;
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unsigned char result_buf[0x400];
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upage_ref_t page_ref;
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void *user_address = (void *)args->X[2];
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if (g_smc_callback_key == 0) {
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return 4;
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}
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if (args->X[1] != g_smc_callback_key) {
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return 5;
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}
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/* Check result size */
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if (args->X[3] > 0x400) {
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return 2;
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}
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args->X[1] = g_smc_callback(result_buf, args->X[3]);
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g_smc_callback_key = 0;
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/* Initialize page reference. */
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if (upage_init(&page_ref, user_address) == 0) {
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return 2;
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}
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/* Copy result output back to user. */
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if (secure_copy_to_user(&page_ref, user_address, result_buf, (size_t)args->X[3]) == 0) {
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return 2;
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}
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return 0;
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}
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uint32_t smc_exp_mod_get_result(void *buf, uint64_t size) {
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if (get_exp_mod_done() != 1) {
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return 3;
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}
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if (size != 0x100) {
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return 2;
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}
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se_get_exp_mod_output(buf, 0x100);
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/* smc_exp_mod is done now. */
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g_is_smc_in_progress = false;
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return 0;
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}
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uint32_t smc_exp_mod(smc_args_t *args) {
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return smc_wrapper_async(args, user_exp_mod, smc_exp_mod_get_result);
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}
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uint32_t smc_get_random_bytes_for_user(smc_args_t *args) {
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return smc_wrapper_sync(args, user_get_random_bytes);
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}
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uint32_t smc_generate_aes_kek(smc_args_t *args) {
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return smc_wrapper_sync(args, user_generate_aes_kek);
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}
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uint32_t smc_load_aes_key(smc_args_t *args) {
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return smc_wrapper_sync(args, user_load_aes_key);
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}
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uint32_t smc_crypt_aes_status_check(void *buf, uint64_t size) {
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/* Buf and size are unused. */
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if (get_crypt_aes_done() != 1) {
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return 3;
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}
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/* smc_crypt_aes is done now. */
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g_is_smc_in_progress = false;
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return 0;
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}
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uint32_t smc_crypt_aes(smc_args_t *args) {
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return smc_wrapper_async(args, user_crypt_aes, smc_crypt_aes_status_check);
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}
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uint32_t smc_generate_specific_aes_key(smc_args_t *args) {
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return smc_wrapper_sync(args, user_generate_specific_aes_key);
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}
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uint32_t smc_compute_cmac(smc_args_t *args) {
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return smc_wrapper_sync(args, user_compute_cmac);
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}
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uint32_t smc_load_rsa_oaep_key(smc_args_t *args) {
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return smc_wrapper_sync(args, user_load_rsa_oaep_key);
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}
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uint32_t smc_decrypt_rsa_private_key(smc_args_t *args) {
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return smc_wrapper_sync(args, user_decrypt_rsa_private_key);
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}
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uint32_t smc_load_secure_exp_mod_key(smc_args_t *args) {
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return smc_wrapper_sync(args, user_load_secure_exp_mod_key);
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}
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uint32_t smc_secure_exp_mod(smc_args_t *args) {
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return smc_wrapper_async(args, user_secure_exp_mod, smc_exp_mod_get_result);
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}
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uint32_t smc_unwrap_rsa_oaep_wrapped_titlekey_get_result(void *buf, uint64_t size) {
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uint64_t *p_sealed_key = (uint64_t *)buf;
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uint8_t rsa_wrapped_titlekey[0x100];
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uint8_t aes_wrapped_titlekey[0x10];
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uint8_t titlekey[0x10];
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uint64_t sealed_titlekey[2];
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if (get_exp_mod_done() != 1) {
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return 3;
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}
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if (size != 0x10) {
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return 2;
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}
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se_get_exp_mod_output(wrapped_titlekey, 0x100);
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if (tkey_rsa_oaep_unwrap(aes_wrapped_titlekey, 0x10, rsa_wrapped_titlekey, 0x100) != 0x10) {
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/* Failed to extract RSA OAEP wrapped key. */
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g_is_smc_in_progress = false;
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return 2;
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}
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tkey_aes_unwrap(titlekey, 0x10, aes_wrapped_titlekey, 0x10);
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seal_titlekey(sealed_titlekey, 0x10, titlekey, 0x10);
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p_sealed_key[0] = sealed_titlekey[0];
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p_sealed_key[1] = sealed_titlekey[1];
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/* smc_unwrap_rsa_oaep_wrapped_titlekey is done now. */
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g_is_smc_in_progress = false;
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return 0;
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}
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uint32_t smc_unwrap_rsa_oaep_wrapped_titlekey(smc_args_t *args) {
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return smc_wrapper_async(args, user_unwrap_rsa_oaep_wrapped_titlekey, smc_unwrap_rsa_oaep_wrapped_titlekey_get_result);
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}
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uint32_t smc_load_titlekey(smc_args_t *args) {
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return smc_wrapper_sync(args, user_load_titlekey);
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}
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uint32_t smc_unwrap_aes_wrapped_titlekey(smc_args_t *args) {
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return smc_wrapper_sync(args, user_unwrap_aes_wrapped_titlekey);
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}
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uint32_t smc_cpu_on(smc_args_t *args) {
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return cpu_on((uint32_t)args->X[1], args->X[2], args->X[3]);
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}
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uint32_t smc_cpu_off(smc_args_t *args) {
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return cpu_off();
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}
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/* Wrapper for cpu_suspend */
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uint32_t cpu_suspend_wrapper(smc_args_t *args) {
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return cpu_suspend(args->X[1], args->X[2], args->X[3]);
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}
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uint32_t smc_cpu_suspend(smc_args_t *args) {
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return smc_wrapper_sync(args, cpu_suspend_wrapper);
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}
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uint32_t smc_get_random_bytes_for_priv(smc_args_t *args) {
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/* This is an interesting SMC. */
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/* The kernel must NEVER be unable to get random bytes, if it needs them */
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/* As such: */
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uint32_t result;
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/* TODO: Make atomic. */
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if (g_is_smc_in_progress) {
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if (args->X[1] > 0x38) {
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return 2;
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}
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/* Retrieve bytes from the cache. */
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size_t num_bytes = (size_t)args->X[1];
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randomcache_getbytes(&args->X[1], num_bytes);
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result = 0;
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} else {
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g_is_smc_in_progress = true;
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/* If the kernel isn't denied service by a usermode SMC, generate fresh random bytes. */
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result = user_get_random_bytes(args);
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/* Also, refill our cache while we have the chance in case we get denied later. */
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randomcache_refill();
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g_is_smc_in_progress = false;
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}
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return result;
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}
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uint32_t smc_read_write_register(smc_args_t *args) {
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uint64_t address = args->X[1];
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uint32_t mask = (uint32_t)(args->X[2]);
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uint32_t value = (uint32_t)(args->X[3]);
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volatile uint32_t *p_mmio = NULL;
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/* Address must be aligned. */
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if (address & 3) {
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return 2;
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}
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/* Check for PMC registers. */
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if (0x7000E400ULL <= address && address <= 0x7000EFFFULL) {
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const uint8_t pmc_whitelist[0x28] = {0xB9, 0xF9, 0x07, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x17, 0x00, 0xC4, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x40, 0x00};
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/* Offset = Address - PMC_BASE */
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uint32_t offset = (uint32_t)(address - 0x7000E400ULL);
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uint32_t wl_ind = (offset >> 5);
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/* If address is whitelisted, allow write. */
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if (wl_ind < sizeof(pmc_whitelist) && (pmc_whitelist[wl_ind] & (1 << ((offset >> 2) & 0x7)))) {
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p_mmio = (volatile uint32_t *)(PMC_BASE + offset);
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} else {
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return 2;
|
|
}
|
|
} else if (mkey_get_revision() >= MASTERKEY_REVISION_400_CURRENT && devices[MMIO_DEVID_MC].paddr <= address && address < devices[MMIO_DEVID_MC].paddr + devices[MMIO_DEVID_MC].size) {
|
|
/* Memory Controller RW supported only on 4.0.0+ */
|
|
const uint8_t mc_whitelist[0x68] = {0x9F, 0x31, 0x30, 0x00, 0xF0, 0xFF, 0xF7, 0x01, 0xCD, 0xFE, 0xC0, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x03, 0x40, 0x73, 0x3E, 0x2F, 0x00, 0x00, 0x6E, 0x30, 0x05, 0x06, 0xB0, 0x71, 0xC8, 0x43, 0x04, 0x80, 0x1F, 0x08, 0x80, 0x03, 0x00, 0x0E, 0x00, 0x08, 0x00, 0xE0, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xF0, 0x03, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x31, 0x00, 0x40, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0xE4, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0xFE, 0x0F, 0x01, 0x00, 0x80, 0x00, 0x00, 0x08, 0x00, 0x00};
|
|
uint32_t offset = (uint32_t)(address - 0x70019000ULL);
|
|
uint32_t wl_ind = (offset >> 5);
|
|
/* If address is whitelisted, allow write. */
|
|
if (wl_ind < sizeof(mc_whitelist) && (mc_whitelist[wl_ind] & (1 << ((offset >> 2) & 0x7)))) {
|
|
p_mmio = (volatile uint32_t *)(mmio_get_device_address(MMIO_DEVID_MC) + offset);
|
|
} else {
|
|
/* These addresses are not allowed by the whitelist. */
|
|
/* They correspond to SMMU DISABLE for the BPMP, and for APB-DMA. */
|
|
/* However, smcReadWriteRegister returns 0 for these addresses despite not actually performing the write. */
|
|
/* This is "probably" to fuck with hackers who got access to smcReadWriteRegister and are trying to get */
|
|
/* control of the BPMP for jamais vu etc., since there's no other reason to return 0 despite failure. */
|
|
if (address == 0x7001923C || address == 0x70019298) {
|
|
return 0;
|
|
}
|
|
return 2;
|
|
}
|
|
}
|
|
|
|
/* Perform actual write. */
|
|
if (p_mmio != NULL) {
|
|
uint32_t old_value;
|
|
/* Write whole value. */
|
|
if (mask == 0xFFFFFFFF) {
|
|
old_value = 0;
|
|
} else {
|
|
old_value = *p_mmio;
|
|
}
|
|
if (mask) {
|
|
*p_mmio = (old_value & ~mask) | (value & mask);
|
|
}
|
|
/* Return old value. */
|
|
args->X[1] = old_value;
|
|
return 0;
|
|
}
|
|
|
|
return 2;
|
|
}
|