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https://github.com/Atmosphere-NX/Atmosphere.git
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29358dc593
Before the MMU is up, all reads/writes must be aligned; the optimized memcpy implementation does not guarantee all reads/writes it performs are aligned. This commit splits the libc impl to be separate for kernel/kernel_ldr, and so now only kernel will use the optimized impl. This is safe, as the MMU is brought up before kernel begins executing.
172 lines
3.8 KiB
ArmAsm
172 lines
3.8 KiB
ArmAsm
/*
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* memset - fill memory with a constant byte
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*
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* Copyright (c) 2012-2020, Arm Limited.
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* SPDX-License-Identifier: MIT
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*/
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/* Assumptions:
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*
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* ARMv8-a, AArch64, Advanced SIMD, unaligned accesses.
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*
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*/
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#include "asmdefs.h"
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#define DC_ZVA_THRESHOLD 512
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#define dstin x0
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#define val x1
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#define valw w1
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#define count x2
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#define dst x3
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#define dstend x4
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#define zva_val x5
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ENTRY (memset)
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bfi valw, valw, 8, 8
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bfi valw, valw, 16, 16
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bfi val, val, 32, 32
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add dstend, dstin, count
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cmp count, 96
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b.hi L(set_long)
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cmp count, 16
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b.hs L(set_medium)
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/* Set 0..15 bytes. */
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tbz count, 3, 1f
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str val, [dstin]
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str val, [dstend, -8]
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ret
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1: tbz count, 2, 2f
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str valw, [dstin]
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str valw, [dstend, -4]
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ret
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2: cbz count, 3f
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strb valw, [dstin]
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tbz count, 1, 3f
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strh valw, [dstend, -2]
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3: ret
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/* Set 16..96 bytes. */
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.p2align 4
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L(set_medium):
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stp val, val, [dstin]
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tbnz count, 6, L(set96)
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stp val, val, [dstend, -16]
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tbz count, 5, 1f
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stp val, val, [dstin, 16]
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stp val, val, [dstend, -32]
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1: ret
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.p2align 4
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/* Set 64..96 bytes. Write 64 bytes from the start and
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32 bytes from the end. */
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L(set96):
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stp val, val, [dstin, 16]
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stp val, val, [dstin, 32]
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stp val, val, [dstin, 48]
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stp val, val, [dstend, -32]
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stp val, val, [dstend, -16]
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ret
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.p2align 4
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L(set_long):
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stp val, val, [dstin]
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#if DC_ZVA_THRESHOLD
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cmp count, DC_ZVA_THRESHOLD
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ccmp val, 0, 0, cs
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bic dst, dstin, 15
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b.eq L(zva_64)
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#else
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bic dst, dstin, 15
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#endif
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/* Small-size or non-zero memset does not use DC ZVA. */
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sub count, dstend, dst
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/*
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* Adjust count and bias for loop. By substracting extra 1 from count,
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* it is easy to use tbz instruction to check whether loop tailing
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* count is less than 33 bytes, so as to bypass 2 unneccesary stps.
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*/
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sub count, count, 64+16+1
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#if DC_ZVA_THRESHOLD
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/* Align loop on 16-byte boundary, this might be friendly to i-cache. */
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nop
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#endif
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1: stp val, val, [dst, 16]
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stp val, val, [dst, 32]
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stp val, val, [dst, 48]
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stp val, val, [dst, 64]!
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subs count, count, 64
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b.hs 1b
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tbz count, 5, 1f /* Remaining count is less than 33 bytes? */
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stp val, val, [dst, 16]
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stp val, val, [dst, 32]
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1: stp val, val, [dstend, -32]
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stp val, val, [dstend, -16]
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ret
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#if DC_ZVA_THRESHOLD
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.p2align 4
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L(zva_64):
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stp val, val, [dst, 16]
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stp val, val, [dst, 32]
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stp val, val, [dst, 48]
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bic dst, dst, 63
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/*
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* Previous memory writes might cross cache line boundary, and cause
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* cache line partially dirty. Zeroing this kind of cache line using
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* DC ZVA will incur extra cost, for it requires loading untouched
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* part of the line from memory before zeoring.
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*
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* So, write the first 64 byte aligned block using stp to force
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* fully dirty cache line.
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*/
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stp val, val, [dst, 64]
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stp val, val, [dst, 80]
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stp val, val, [dst, 96]
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stp val, val, [dst, 112]
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sub count, dstend, dst
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/*
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* Adjust count and bias for loop. By substracting extra 1 from count,
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* it is easy to use tbz instruction to check whether loop tailing
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* count is less than 33 bytes, so as to bypass 2 unneccesary stps.
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*/
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sub count, count, 128+64+64+1
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add dst, dst, 128
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nop
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/* DC ZVA sets 64 bytes each time. */
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1: dc zva, dst
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add dst, dst, 64
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subs count, count, 64
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b.hs 1b
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/*
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* Write the last 64 byte aligned block using stp to force fully
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* dirty cache line.
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*/
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stp val, val, [dst, 0]
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stp val, val, [dst, 16]
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stp val, val, [dst, 32]
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stp val, val, [dst, 48]
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tbz count, 5, 1f /* Remaining count is less than 33 bytes? */
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stp val, val, [dst, 64]
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stp val, val, [dst, 80]
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1: stp val, val, [dstend, -32]
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stp val, val, [dstend, -16]
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ret
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#endif
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END (memset)
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