mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
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f66b41c027
exo2: Implement uncompressor stub and boot code up to Main(). exo2: implement some more init (uart/gic) exo2: implement more of init exo2: improve reg api, add keyslot flag setters exo2: implement se aes decryption/enc exo2: fix bugs in loader stub/mmu mappings exo2: start skeletoning bootconfig/global context types arch: fix makefile flags exo2: implement through master key derivation exo2: implement device master keygen exo2: more init through start of SetupSocSecurity exo2: implement pmc secure scratch management se: implement sticky bit validation libexosphere: fix building for arm32 libexo: fix makefile flags libexo: support building for arm64/arm sc7fw: skeleton binary sc7fw: skeleton a little more sc7fw: implement all non-dram functionality exo2: fix DivideUp error sc7fw: implement more dram code, fix reg library errors sc7fw: complete sc7fw impl. exo2: skeleton the rest of SetupSocSecurity exo2: implement fiq interrupt handler exo2: implement all exception handlers exo2: skeleton the entire smc api, implement the svc invoker exo2: implement rest of SetupSocSecurity exo2: correct slave security errors exo2: fix register definition exo2: minor fixes
326 lines
9.1 KiB
ArmAsm
326 lines
9.1 KiB
ArmAsm
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* Some macros taken from https://github.com/ARM-software/arm-trusted-firmware/blob/master/include/common/aarch64/asm_macros.S */
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/*
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* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* Declare the exception vector table, enforcing it is aligned on a
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* 2KB boundary, as required by the ARMv8 architecture.
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* Use zero bytes as the fill value to be stored in the padding bytes
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* so that it inserts illegal AArch64 instructions. This increases
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* security, robustness and potentially facilitates debugging.
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*/
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.macro vector_base label, section_name=.vectors
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.section \section_name, "ax"
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.align 11, 0
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\label:
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.endm
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/*
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* Create an entry in the exception vector table, enforcing it is
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* aligned on a 128-byte boundary, as required by the ARMv8 architecture.
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* Use zero bytes as the fill value to be stored in the padding bytes
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* so that it inserts illegal AArch64 instructions. This increases
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* security, robustness and potentially facilitates debugging.
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*/
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.macro vector_entry label, section_name=.vectors
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.cfi_sections .debug_frame
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.section \section_name, "ax"
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.align 7, 0
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.type \label, %function
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.func \label
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.cfi_startproc
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\label:
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.endm
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/*
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* This macro verifies that the given vector doesnt exceed the
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* architectural limit of 32 instructions. This is meant to be placed
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* immediately after the last instruction in the vector. It takes the
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* vector entry as the parameter
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*/
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.macro check_vector_size since
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.endfunc
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.cfi_endproc
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.if (. - \since) > (32 * 4)
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.error "Vector exceeds 32 instructions"
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.endif
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.endm
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/* Actual Vectors for Secure Monitor. */
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.global _ZN3ams6secmon16ExceptionVectorsEv
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vector_base _ZN3ams6secmon16ExceptionVectorsEv
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/* Current EL, SP0 */
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vector_entry synch_sp0
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/* Branch to the exception handler. */
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b _ZN3ams6secmon26UnexpectedExceptionHandlerEv
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.endfunc
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.cfi_endproc
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_ZN3ams6secmon26UnexpectedExceptionHandlerEv:
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/* Load the ErrorInfo scratch. */
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ldr x0, =0x1F004AC40
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/* Write ErrorInfo_UnknownAbort to it. */
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ldr w1, =0x07F00010
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str w1, [x0]
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/* Perform an error reboot. */
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b _ZN3ams6secmon11ErrorRebootEv
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vector_entry irq_sp0
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/* An unexpected exception was taken. */
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b _ZN3ams6secmon26UnexpectedExceptionHandlerEv
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check_vector_size irq_sp0
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vector_entry fiq_sp0
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/* An unexpected exception was taken. */
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b _ZN3ams6secmon26UnexpectedExceptionHandlerEv
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check_vector_size fiq_sp0
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vector_entry serror_sp0
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/* An unexpected exception was taken. */
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b _ZN3ams6secmon26UnexpectedExceptionHandlerEv
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check_vector_size serror_sp0
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/* Current EL, SPx */
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vector_entry synch_spx
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/* An unexpected exception was taken. */
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b _ZN3ams6secmon26UnexpectedExceptionHandlerEv
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check_vector_size synch_spx
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vector_entry irq_spx
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/* An unexpected exception was taken. */
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b _ZN3ams6secmon26UnexpectedExceptionHandlerEv
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check_vector_size irq_spx
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vector_entry fiq_spx
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/* An unexpected exception was taken. */
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b _ZN3ams6secmon26UnexpectedExceptionHandlerEv
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check_vector_size fiq_spx
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vector_entry serror_spx
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/* An unexpected exception was taken. */
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b _ZN3ams6secmon26UnexpectedExceptionHandlerEv
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check_vector_size serror_spx
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/* Lower EL, A64 */
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vector_entry synch_a64
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/* Check whether the exception is an SMC. If it's not, take the unexpected handler. */
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stp x29, x30, [sp, #-0x10]!
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mrs x30, esr_el3
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lsr w29, w30, #26
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cmp w29, #0x17
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ldp x29, x30, [sp], #0x10
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b.ne _ZN3ams6secmon26UnexpectedExceptionHandlerEv
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/* Save x29 and x30. */
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stp x29, x30, [sp, #-0x10]!
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/* Get the current core. */
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mrs x29, mpidr_el1
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and x29, x29, #3
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/* If we're not on core 3, take the core0-2 handler. */
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cmp x29, #3
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b.ne _ZN3ams6secmon25HandleSmcExceptionCore012Ev
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/* Handle the smc. */
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bl _ZN3ams6secmon18HandleSmcExceptionEv
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/* Return. */
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ldp x29, x30, [sp], #0x10
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eret
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check_vector_size synch_a64
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vector_entry irq_a64
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/* An unexpected exception was taken. */
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b _ZN3ams6secmon26UnexpectedExceptionHandlerEv
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check_vector_size irq_a64
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vector_entry fiq_a64
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/* Save X29, X30. */
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stp x29, x30, [sp, #-0x10]!
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/* Get the current core ID, ensure it's core 3. */
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mrs x29, mpidr_el1
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and x29, x29, #3
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cmp x29, #3
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b.ne _ZN3ams6secmon26UnexpectedExceptionHandlerEv
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/* Save x26-x28, x18. */
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stp x28, x18, [sp, #-0x10]!
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stp x26, x27, [sp, #-0x10]!
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/* Set x18 to the global data region. */
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ldr x18, =0x1F01FA000
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/* Handle the fiq exception. */
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bl _ZN3ams6secmon18HandleFiqExceptionEv
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/* Restore registers. */
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ldp x26, x27, [sp], #0x10
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ldp x28, x18, [sp], #0x10
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ldp x29, x30, [sp], #0x10
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/* Return. */
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eret
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check_vector_size fiq_a64
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vector_entry serror_a64
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/* An unexpected exception was taken. */
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b _ZN3ams6secmon26UnexpectedExceptionHandlerEv
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.endfunc
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.cfi_endproc
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_ZN3ams6secmon25HandleSmcExceptionCore012Ev:
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/* Acquire exclusive access to the common smc stack. */
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stp x4, x5, [sp, #-0x10]!
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stp x2, x3, [sp, #-0x10]!
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stp x0, x1, [sp, #-0x10]!
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bl _ZN3ams6secmon25AcquireCommonSmcStackLockEv
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ldp x0, x1, [sp], #0x10
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ldp x2, x3, [sp], #0x10
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ldp x4, x5, [sp], #0x10
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/* Pivot to use the common smc stack. */
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mov x30, sp
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ldr x29, =0x1F01F6E80
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mov sp, x29
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stp x29, x30, [sp, #-0x10]!
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/* Handle the SMC. */
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bl _ZN3ams6secmon18HandleSmcExceptionEv
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/* Restore our core-specific stack. */
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ldp x29, x30, [sp], #0x10
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mov x30, sp
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/* Release our exclusive access to the common smc stack. */
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stp x0, x1, [sp, #-0x10]!
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bl _ZN3ams6secmon25ReleaseCommonSmcStackLockEv
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ldp x0, x1, [sp], #0x10
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/* Return. */
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ldp x29, x30, [sp], #0x10
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eret
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/* Lower EL, A32 */
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vector_entry synch_a32
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/* An unexpected exception was taken. */
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b _ZN3ams6secmon26UnexpectedExceptionHandlerEv
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check_vector_size synch_a32
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vector_entry irq_a32
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/* An unexpected exception was taken. */
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b _ZN3ams6secmon26UnexpectedExceptionHandlerEv
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.endfunc
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.cfi_endproc
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_ZN3ams6secmon18HandleSmcExceptionEv:
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/* Save registers. */
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stp x29, x30, [sp, #-0x10]!
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stp x18, x19, [sp, #-0x10]!
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stp x16, x17, [sp, #-0x10]!
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stp x14, x15, [sp, #-0x10]!
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stp x12, x13, [sp, #-0x10]!
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stp x10, x11, [sp, #-0x10]!
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stp x8, x9, [sp, #-0x10]!
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stp x6, x7, [sp, #-0x10]!
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stp x4, x5, [sp, #-0x10]!
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stp x2, x3, [sp, #-0x10]!
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stp x0, x1, [sp, #-0x10]!
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/* Set x18 to the global data region. */
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ldr x18, =0x1F01FA000
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/* Get esr. */
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mrs x0, esr_el3
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and x0, x0, #0xFFFF
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/* Get the function arguments. */
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mov x1, sp
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/* Invoke the smc handler. */
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bl _ZN3ams6secmon3smc9HandleSmcEiRNS1_12SmcArgumentsE
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/* Restore registers. */
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ldp x0, x1, [sp], #0x10
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ldp x2, x3, [sp], #0x10
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ldp x4, x5, [sp], #0x10
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ldp x6, x7, [sp], #0x10
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ldp x8, x9, [sp], #0x10
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ldp x10, x11, [sp], #0x10
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ldp x12, x13, [sp], #0x10
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ldp x14, x15, [sp], #0x10
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ldp x16, x17, [sp], #0x10
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ldp x18, x19, [sp], #0x10
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ldp x29, x30, [sp], #0x10
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ret
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vector_entry fiq_a32
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/* Handle fiq from a32 the same as fiq from a64. */
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b fiq_a64
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.endfunc
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.cfi_endproc
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_ZN3ams6secmon18HandleFiqExceptionEv:
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/* Save registers. */
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stp x29, x30, [sp, #-0x10]!
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stp x24, x25, [sp, #-0x10]!
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stp x22, x23, [sp, #-0x10]!
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stp x20, x21, [sp, #-0x10]!
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stp x18, x19, [sp, #-0x10]!
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stp x16, x17, [sp, #-0x10]!
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stp x14, x15, [sp, #-0x10]!
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stp x12, x13, [sp, #-0x10]!
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stp x10, x11, [sp, #-0x10]!
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stp x8, x9, [sp, #-0x10]!
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stp x6, x7, [sp, #-0x10]!
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stp x4, x5, [sp, #-0x10]!
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stp x2, x3, [sp, #-0x10]!
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stp x0, x1, [sp, #-0x10]!
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/* Invoke the interrupt handler. */
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bl _ZN3ams6secmon15HandleInterruptEv
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/* Restore registers. */
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ldp x0, x1, [sp], #0x10
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ldp x2, x3, [sp], #0x10
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ldp x4, x5, [sp], #0x10
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ldp x6, x7, [sp], #0x10
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ldp x8, x9, [sp], #0x10
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ldp x10, x11, [sp], #0x10
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ldp x12, x13, [sp], #0x10
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ldp x14, x15, [sp], #0x10
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ldp x16, x17, [sp], #0x10
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ldp x18, x19, [sp], #0x10
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ldp x20, x21, [sp], #0x10
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ldp x22, x23, [sp], #0x10
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ldp x24, x25, [sp], #0x10
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ldp x29, x30, [sp], #0x10
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ret
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vector_entry serror_a32
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/* An unexpected exception was taken. */
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b _ZN3ams6secmon26UnexpectedExceptionHandlerEv
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check_vector_size serror_a32
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/* Instantiate the literal pool for the exception vectors. */
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.ltorg
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