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https://github.com/Atmosphere-NX/Atmosphere.git
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547 lines
26 KiB
C++
547 lines
26 KiB
C++
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <exosphere.hpp>
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#include "../secmon_cache.hpp"
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#include "../secmon_cpu_context.hpp"
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#include "../secmon_error.hpp"
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#include "../secmon_misc.hpp"
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#include "secmon_smc_power_management.hpp"
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#include "secmon_smc_se_lock.hpp"
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#include "sc7fw_bin.h"
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namespace ams::secmon {
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/* Declare assembly functionality. */
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void *GetCoreExceptionStackVirtual();
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}
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namespace ams::secmon::smc {
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/* Declare assembly power-management functionality. */
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void PivotStackAndInvoke(void *stack, void (*function)());
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void FinalizePowerOff();
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namespace {
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constexpr inline const uintptr_t PMC = MemoryRegionVirtualDevicePmc.GetAddress();
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constexpr inline const uintptr_t APB_MISC = MemoryRegionVirtualDeviceApbMisc.GetAddress();
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constexpr inline const uintptr_t GPIO = MemoryRegionVirtualDeviceGpio.GetAddress();
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constexpr inline const uintptr_t CLK_RST = MemoryRegionVirtualDeviceClkRst.GetAddress();
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constexpr inline const uintptr_t EVP = secmon::MemoryRegionVirtualDeviceExceptionVectors.GetAddress();
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constexpr inline const uintptr_t FLOW_CTLR = MemoryRegionVirtualDeviceFlowController.GetAddress();
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constexpr inline const uintptr_t AHB_ARBC = MemoryRegionVirtualDeviceSystem.GetAddress();
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constexpr inline uintptr_t CommonSmcStackTop = MemoryRegionVirtualTzramVolatileData.GetEndAddress() - (0x80 * (NumCores - 1));
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enum PowerStateType {
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PowerStateType_StandBy = 0,
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PowerStateType_PowerDown = 1,
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};
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enum PowerStateId {
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PowerStateId_Sc7 = 27,
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};
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/* http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf Page 46 */
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struct SuspendCpuPowerState {
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using StateId = util::BitPack32::Field< 0, 16, PowerStateId>;
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using StateType = util::BitPack32::Field<16, 1, PowerStateType>;
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using PowerLevel = util::BitPack32::Field<24, 2, u32>;
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};
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constinit bool g_charger_hi_z_mode_enabled = false;
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constinit const reg::BitsMask CpuPowerGateStatusMasks[NumCores] = {
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PMC_REG_BITS_MASK(PWRGATE_STATUS_CE0),
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PMC_REG_BITS_MASK(PWRGATE_STATUS_CE1),
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PMC_REG_BITS_MASK(PWRGATE_STATUS_CE2),
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PMC_REG_BITS_MASK(PWRGATE_STATUS_CE3),
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};
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constinit const APBDEV_PMC_PWRGATE_TOGGLE_PARTID CpuPowerGateTogglePartitionIds[NumCores] = {
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APBDEV_PMC_PWRGATE_TOGGLE_PARTID_CE0,
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APBDEV_PMC_PWRGATE_TOGGLE_PARTID_CE1,
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APBDEV_PMC_PWRGATE_TOGGLE_PARTID_CE2,
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APBDEV_PMC_PWRGATE_TOGGLE_PARTID_CE3,
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};
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bool IsCpuPoweredOn(const reg::BitsMask mask) {
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return reg::HasValue(PMC + APBDEV_PMC_PWRGATE_STATUS, REG_BITS_VALUE_FROM_MASK(mask, APBDEV_PMC_PWRGATE_STATUS_STATUS_ON));
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}
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void PowerOnCpu(const reg::BitsMask mask, u32 toggle_partid) {
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/* If the cpu is already on, we have nothing to do. */
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if (IsCpuPoweredOn(mask)) {
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return;
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}
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/* Wait until nothing is being powergated. */
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int timeout = 5000;
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while (true) {
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if (reg::HasValue(PMC + APBDEV_PMC_PWRGATE_TOGGLE, PMC_REG_BITS_ENUM(PWRGATE_TOGGLE_START, DISABLE))) {
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break;
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}
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util::WaitMicroSeconds(1);
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if ((--timeout) < 0) {
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/* NOTE: Nintendo doesn't do any error handling here... */
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return;
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}
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}
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/* Toggle on the cpu partition. */
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reg::Write(PMC + APBDEV_PMC_PWRGATE_TOGGLE, PMC_REG_BITS_ENUM (PWRGATE_TOGGLE_START, ENABLE),
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PMC_REG_BITS_VALUE(PWRGATE_TOGGLE_PARTID, toggle_partid));
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/* Wait up to 5000 us for the powergate to complete. */
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timeout = 5000;
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while (true) {
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if (IsCpuPoweredOn(mask)) {
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break;
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}
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util::WaitMicroSeconds(1);
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if ((--timeout) < 0) {
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/* NOTE: Nintendo doesn't do any error handling here... */
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return;
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}
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}
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}
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void ResetCpu(int which_core) {
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reg::Write(CLK_RST + CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET, REG_BITS_VALUE(which_core + 0x00, 1, 1), /* CPURESETn */
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REG_BITS_VALUE(which_core + 0x10, 1, 1)); /* CORERESETn */
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}
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void StartCpu(int which_core) {
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reg::Write(CLK_RST + CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR, REG_BITS_VALUE(which_core + 0x00, 1, 1), /* CPURESETn */
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REG_BITS_VALUE(which_core + 0x10, 1, 1)); /* CORERESETn */
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}
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void PowerOffCpu() {
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/* Get the current core id. */
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const auto core_id = hw::GetCurrentCoreId();
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/* Configure the flow controller to prepare for shutting down the current core. */
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flow::SetCpuCsr(core_id, FLOW_CTLR_CPUN_CSR_ENABLE_EXT_POWERGATE_CPU_ONLY);
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flow::SetHaltCpuEvents(core_id, false);
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flow::SetCc4Ctrl(core_id, 0);
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/* Save the core's context for restoration on next power-on. */
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SaveDebugRegisters();
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SetCoreOff();
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/* Ensure there are no pending memory transactions prior to our power-down. */
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FlushEntireDataCache();
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/* Finalize our powerdown and wait for an interrupt. */
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FinalizePowerOff();
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}
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void ValidateSocStateForSuspend() {
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/* Validate that all other cores are off. */
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AMS_ABORT_UNLESS(reg::HasValue(PMC + APBDEV_PMC_PWRGATE_STATUS, PMC_REG_BITS_VALUE(PWRGATE_STATUS_CE123, 0)));
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/* Validate that the bpmp is appropriately halted. */
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const bool jtag = IsJtagEnabled();
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AMS_ABORT_UNLESS(reg::Read(FLOW_CTLR + FLOW_CTLR_HALT_COP_EVENTS) == reg::Encode(FLOW_REG_BITS_ENUM (HALT_COP_EVENTS_MODE, FLOW_MODE_STOP),
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FLOW_REG_BITS_ENUM_SEL(HALT_COP_EVENTS_JTAG, jtag, ENABLED, DISABLED)));
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/* Further validations aren't guaranteed on < 6.0.0. */
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if (GetTargetFirmware() < TargetFirmware_6_0_0) {
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return;
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}
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/* Validate that USB2, APB-DMA, AHB-DMA are held in reset. */
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AMS_ABORT_UNLESS(reg::HasValue(CLK_RST + CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_REG_BITS_ENUM(RST_DEVICES_H_SWR_USB2_RST, ENABLE),
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CLK_RST_REG_BITS_ENUM(RST_DEVICES_H_SWR_APBDMA_RST, ENABLE),
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CLK_RST_REG_BITS_ENUM(RST_DEVICES_H_SWR_AHBDMA_RST, ENABLE)));
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/* Validate that USBD is held in reset. */
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AMS_ABORT_UNLESS(reg::HasValue(CLK_RST + CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_REG_BITS_ENUM(RST_DEVICES_L_SWR_USBD_RST, ENABLE)));
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/* Validate that AHB-DMA, USB, USB2, COP are not allowed to arbitrate on the AHB. */
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AMS_ABORT_UNLESS(reg::HasValue(AHB_ARBC + AHB_ARBITRATION_DISABLE, AHB_REG_BITS_ENUM(ARBITRATION_DISABLE_COP, DISABLE),
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AHB_REG_BITS_ENUM(ARBITRATION_DISABLE_AHBDMA, DISABLE),
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AHB_REG_BITS_ENUM(ARBITRATION_DISABLE_USB, DISABLE),
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AHB_REG_BITS_ENUM(ARBITRATION_DISABLE_USB2, DISABLE)));
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/* Validate that the GPIO controller has clock enabled. */
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AMS_ABORT_UNLESS(reg::HasValue(CLK_RST + CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_REG_BITS_ENUM(CLK_OUT_ENB_L_CLK_ENB_GPIO, ENABLE)));
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/* Validate that both FUSE and KFUSE have clock enabled. */
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AMS_ABORT_UNLESS(reg::HasValue(CLK_RST + CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_REG_BITS_ENUM(CLK_OUT_ENB_H_CLK_ENB_FUSE, ENABLE),
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CLK_RST_REG_BITS_ENUM(CLK_OUT_ENB_H_CLK_ENB_KFUSE, ENABLE)));
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/* Validate that all of IRAM has clock enabled. */
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AMS_ABORT_UNLESS(reg::HasValue(CLK_RST + CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_REG_BITS_ENUM(CLK_OUT_ENB_U_CLK_ENB_IRAMA, ENABLE),
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CLK_RST_REG_BITS_ENUM(CLK_OUT_ENB_U_CLK_ENB_IRAMB, ENABLE),
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CLK_RST_REG_BITS_ENUM(CLK_OUT_ENB_U_CLK_ENB_IRAMC, ENABLE),
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CLK_RST_REG_BITS_ENUM(CLK_OUT_ENB_U_CLK_ENB_IRAMD, ENABLE)));
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/* Validate that ACTMON has clock enabled. */
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AMS_ABORT_UNLESS(reg::HasValue(CLK_RST + CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_REG_BITS_ENUM(CLK_OUT_ENB_V_CLK_ENB_ACTMON, ENABLE)));
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/* Validate that ENTROPY has clock enabled. */
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AMS_ABORT_UNLESS(reg::HasValue(CLK_RST + CLK_RST_CONTROLLER_CLK_OUT_ENB_W, CLK_RST_REG_BITS_ENUM(CLK_OUT_ENB_W_CLK_ENB_ENTROPY, ENABLE)));
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}
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void GenerateCryptographicallyRandomBytes(void * const dst, int size) {
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/* Flush the region we're about to fill to ensure consistency with the SE. */
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hw::FlushDataCache(dst, size);
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hw::DataSynchronizationBarrierInnerShareable();
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/* Generate random bytes. */
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se::GenerateRandomBytes(dst, size);
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hw::DataSynchronizationBarrierInnerShareable();
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/* Flush to ensure the CPU sees consistent data for the region. */
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hw::FlushDataCache(dst, size);
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hw::DataSynchronizationBarrierInnerShareable();
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}
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void SaveSecureContextForErista() {
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/* Generate a random key source. */
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util::AlignedBuffer<hw::DataCacheLineSize, se::AesBlockSize> key_source;
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GenerateCryptographicallyRandomBytes(key_source, se::AesBlockSize);
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const u32 * const key_source_32 = reinterpret_cast<const u32 *>(static_cast<u8 *>(key_source));
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/* Ensure that the key source registers are not locked. */
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AMS_ABORT_UNLESS(pmc::GetSecureRegisterLockState(pmc::SecureRegister_KeySourceReadWrite) != pmc::LockState::Locked);
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/* Write the key source, lock writes to the key source, and verify that the key source is write-locked. */
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reg::Write(PMC + APBDEV_PMC_SECURE_SCRATCH24, key_source_32[0]);
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reg::Write(PMC + APBDEV_PMC_SECURE_SCRATCH25, key_source_32[1]);
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reg::Write(PMC + APBDEV_PMC_SECURE_SCRATCH26, key_source_32[2]);
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reg::Write(PMC + APBDEV_PMC_SECURE_SCRATCH27, key_source_32[3]);
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pmc::LockSecureRegister(pmc::SecureRegister_KeySourceWrite);
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AMS_ABORT_UNLESS(pmc::GetSecureRegisterLockState(pmc::SecureRegister_KeySourceWrite) == pmc::LockState::Locked);
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/* Verify the key source is correct in registers, and read-lock the key source registers. */
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AMS_ABORT_UNLESS(reg::Read(PMC + APBDEV_PMC_SECURE_SCRATCH24) == key_source_32[0]);
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AMS_ABORT_UNLESS(reg::Read(PMC + APBDEV_PMC_SECURE_SCRATCH25) == key_source_32[1]);
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AMS_ABORT_UNLESS(reg::Read(PMC + APBDEV_PMC_SECURE_SCRATCH26) == key_source_32[2]);
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AMS_ABORT_UNLESS(reg::Read(PMC + APBDEV_PMC_SECURE_SCRATCH27) == key_source_32[3]);
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pmc::LockSecureRegister(pmc::SecureRegister_KeySourceRead);
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/* Ensure that the key source registers are locked. */
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AMS_ABORT_UNLESS(pmc::GetSecureRegisterLockState(pmc::SecureRegister_KeySourceReadWrite) == pmc::LockState::Locked);
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/* Generate a random kek into keyslot 2. */
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se::SetRandomKey(pkg1::AesKeySlot_TzramSaveKek);
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/* Verify that the se is in a validate state, context save, and validate again. */
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{
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se::ValidateErrStatus();
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ON_SCOPE_EXIT { se::ValidateErrStatus(); };
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{
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/* Transition to non-secure mode for the duration of the context save operation. */
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se::SetSecure(false);
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ON_SCOPE_EXIT { se::SetSecure(true); };
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/* Get a pointer to the context storage. */
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se::Context * const context = MemoryRegionVirtualDramSecureDataStoreSecurityEngineState.GetPointer<se::Context>();
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static_assert(MemoryRegionVirtualDramSecureDataStoreSecurityEngineState.GetSize() == sizeof(*context));
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/* Save the context. */
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se::SaveContext(context);
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/* Ensure that the cpu sees consistent data. */
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hw::FlushDataCache(context, sizeof(*context));
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hw::DataSynchronizationBarrierInnerShareable();
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/* Write the context pointer to pmc scratch, so that the bootrom will restore it on wake. */
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reg::Write(PMC + APBDEV_PMC_SCRATCH43, MemoryRegionPhysicalDramSecureDataStoreSecurityEngineState.GetAddress());
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}
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}
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/* Clear keyslot 3, and then derive the save key. */
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se::ClearAesKeySlot(pkg1::AesKeySlot_TzramSaveKey);
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se::SetEncryptedAesKey256(pkg1::AesKeySlot_TzramSaveKey, pkg1::AesKeySlot_TzramSaveKek, key_source, se::AesBlockSize);
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/* Declare a temporary block to be used as both iv and mac. */
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u32 temp_block[se::AesBlockSize / sizeof(u32)] = {};
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/* Ensure that the SE sees consistent data for tzram. */
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const void * const tzram_save_src = MemoryRegionVirtualTzramReadOnlyAlias.GetPointer<u8>() + MemoryRegionVirtualTzramVolatileData.GetSize() + MemoryRegionVirtualTzramVolatileStack.GetSize();
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void * const tzram_save_dst = MemoryRegionVirtualIramSc7Work.GetPointer<void>();
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constexpr size_t TzramSaveSize = MemoryRegionVirtualDramSecureDataStoreTzram.GetSize();
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hw::FlushDataCache(tzram_save_src, TzramSaveSize);
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hw::FlushDataCache(tzram_save_dst, TzramSaveSize);
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hw::DataSynchronizationBarrierInnerShareable();
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/* Encrypt tzram using our random key. */
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se::EncryptAes256Cbc(tzram_save_dst, TzramSaveSize, pkg1::AesKeySlot_TzramSaveKey, tzram_save_src, TzramSaveSize, temp_block, se::AesBlockSize);
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hw::FlushDataCache(tzram_save_dst, TzramSaveSize);
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hw::DataSynchronizationBarrierInnerShareable();
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/* Copy the data from work space to the secure storage destination. */
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void * const tzram_store_dst = MemoryRegionVirtualDramSecureDataStoreTzram.GetPointer<void>();
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std::memcpy(tzram_store_dst, tzram_save_dst, TzramSaveSize);
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hw::FlushDataCache(tzram_store_dst, TzramSaveSize);
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hw::DataSynchronizationBarrierInnerShareable();
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/* Compute cmac of tzram into our temporary block. */
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se::ComputeAes256Cmac(temp_block, se::AesBlockSize, pkg1::AesKeySlot_TzramSaveKey, tzram_save_src, TzramSaveSize);
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/* Ensure that the cmac registers are not locked. */
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AMS_ABORT_UNLESS(pmc::GetSecureRegisterLockState(pmc::SecureRegister_CmacReadWrite) != pmc::LockState::Locked);
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/* Write the cmac, lock writes to the cmac, and verify that the cmac is write-locked. */
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reg::Write(PMC + APBDEV_PMC_SECURE_SCRATCH112, temp_block[0]);
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reg::Write(PMC + APBDEV_PMC_SECURE_SCRATCH113, temp_block[1]);
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reg::Write(PMC + APBDEV_PMC_SECURE_SCRATCH114, temp_block[2]);
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reg::Write(PMC + APBDEV_PMC_SECURE_SCRATCH115, temp_block[3]);
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pmc::LockSecureRegister(pmc::SecureRegister_CmacWrite);
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AMS_ABORT_UNLESS(pmc::GetSecureRegisterLockState(pmc::SecureRegister_CmacWrite) == pmc::LockState::Locked);
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/* Verify the key source is correct in registers, and read-lock the key source registers. */
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AMS_ABORT_UNLESS(reg::Read(PMC + APBDEV_PMC_SECURE_SCRATCH112) == temp_block[0]);
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AMS_ABORT_UNLESS(reg::Read(PMC + APBDEV_PMC_SECURE_SCRATCH113) == temp_block[1]);
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AMS_ABORT_UNLESS(reg::Read(PMC + APBDEV_PMC_SECURE_SCRATCH114) == temp_block[2]);
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AMS_ABORT_UNLESS(reg::Read(PMC + APBDEV_PMC_SECURE_SCRATCH115) == temp_block[3]);
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pmc::LockSecureRegister(pmc::SecureRegister_CmacRead);
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/* Ensure that the key source registers are locked. */
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AMS_ABORT_UNLESS(pmc::GetSecureRegisterLockState(pmc::SecureRegister_CmacReadWrite) == pmc::LockState::Locked);
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}
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void SaveSecureContextForMariko() {
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/* Save security engine context to TZRAM SE carveout (inaccessible to cpu). */
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se::SaveContextAutomatic();
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/* Save TZRAM to shadow-TZRAM in always-on power domain. */
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se::SaveTzramAutomatic();
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}
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void SaveSecureContext() {
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const auto soc_type = GetSocType();
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if (soc_type == fuse::SocType_Erista) {
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SaveSecureContextForErista();
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} else /* if (soc_type == fuse::SocType_Mariko) */ {
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SaveSecureContextForMariko();
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}
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}
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void LoadAndStartSc7BpmpFirmware() {
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/* Set BPMP reset. */
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reg::Write(CLK_RST + CLK_RST_CONTROLLER_RST_DEV_L_SET, CLK_RST_REG_BITS_ENUM(RST_DEV_L_SET_SET_COP_RST, ENABLE));
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/* Set the PMC as insecure, so that the BPMP firmware can access it. */
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reg::ReadWrite(APB_MISC + APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0, SLAVE_SECURITY_REG_BITS_ENUM(0, PMC, DISABLE));
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/* Set the exception vectors for the bpmp. RESET should point to RESET, all others should point to generic exception/panic. */
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constexpr const u32 Sc7FirmwareResetVector = static_cast<u32>(MemoryRegionPhysicalIramSc7Firmware.GetAddress() + 0x0);
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constexpr const u32 Sc7FirmwarePanicVector = static_cast<u32>(MemoryRegionPhysicalIramSc7Firmware.GetAddress() + 0x4);
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reg::Write(EVP + EVP_COP_RESET_VECTOR, Sc7FirmwareResetVector);
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reg::Write(EVP + EVP_COP_UNDEF_VECTOR, Sc7FirmwarePanicVector);
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reg::Write(EVP + EVP_COP_SWI_VECTOR, Sc7FirmwarePanicVector);
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reg::Write(EVP + EVP_COP_PREFETCH_ABORT_VECTOR, Sc7FirmwarePanicVector);
|
|
reg::Write(EVP + EVP_COP_DATA_ABORT_VECTOR, Sc7FirmwarePanicVector);
|
|
reg::Write(EVP + EVP_COP_RSVD_VECTOR, Sc7FirmwarePanicVector);
|
|
reg::Write(EVP + EVP_COP_IRQ_VECTOR, Sc7FirmwarePanicVector);
|
|
reg::Write(EVP + EVP_COP_FIQ_VECTOR, Sc7FirmwarePanicVector);
|
|
|
|
/* Disable activity monitor bpmp monitoring, so that we don't panic upon bpmp wake. */
|
|
actmon::StopMonitoringBpmp();
|
|
|
|
/* Load the bpmp firmware. */
|
|
void * const sc7fw_load_address = MemoryRegionVirtualIramSc7Firmware.GetPointer<void>();
|
|
std::memcpy(sc7fw_load_address, sc7fw_bin, sc7fw_bin_size);
|
|
hw::FlushDataCache(sc7fw_load_address, sc7fw_bin_size);
|
|
hw::DataSynchronizationBarrierInnerShareable();
|
|
|
|
/* Ensure that the bpmp firmware was loaded. */
|
|
AMS_ABORT_UNLESS(crypto::IsSameBytes(sc7fw_load_address, sc7fw_bin, sc7fw_bin_size));
|
|
|
|
/* Clear BPMP reset. */
|
|
reg::Write(CLK_RST + CLK_RST_CONTROLLER_RST_DEV_L_CLR, CLK_RST_REG_BITS_ENUM(RST_DEV_L_CLR_CLR_COP_RST, ENABLE));
|
|
|
|
/* Start the bpmp. */
|
|
reg::Write(FLOW_CTLR + FLOW_CTLR_HALT_COP_EVENTS, FLOW_REG_BITS_ENUM(HALT_COP_EVENTS_MODE, FLOW_MODE_NONE));
|
|
}
|
|
|
|
void SaveSecureContextAndSuspend() {
|
|
/* Ensure there are no pending memory transactions before we continue */
|
|
FlushEntireDataCache();
|
|
hw::DataSynchronizationBarrierInnerShareable();
|
|
|
|
/* Save all secure context (security engine state + tzram). */
|
|
SaveSecureContext();
|
|
|
|
/* Load and start the sc7 firmware on the bpmp. */
|
|
if (GetTargetFirmware() >= TargetFirmware_2_0_0) {
|
|
LoadAndStartSc7BpmpFirmware();
|
|
}
|
|
|
|
/* Log our suspension. */
|
|
/* NOTE: Nintendo only does this on dev, but we will always do it. */
|
|
if (true /* !pkg1::IsProduction() */) {
|
|
log::SendText("OYASUMI\n", 8);
|
|
}
|
|
|
|
/* If we're on erista, configure the bootrom to allow our custom warmboot firmware. */
|
|
if (GetSocType() == fuse::SocType_Erista) {
|
|
reg::Write(PMC + APBDEV_PMC_SCRATCH31, 0x2202E012);
|
|
reg::Write(PMC + APBDEV_PMC_SCRATCH32, 0x6001DC28);
|
|
}
|
|
|
|
/* Finalize our powerdown and wait for an interrupt. */
|
|
FinalizePowerOff();
|
|
}
|
|
|
|
SmcResult SuspendCpuImpl(SmcArguments &args) {
|
|
/* Decode arguments. */
|
|
const util::BitPack32 power_state = { static_cast<u32>(args.r[1]) };
|
|
const uintptr_t entry_point = args.r[2];
|
|
const uintptr_t context_id = args.r[3];
|
|
|
|
const auto state_type = power_state.Get<SuspendCpuPowerState::StateType>();
|
|
const auto state_id = power_state.Get<SuspendCpuPowerState::StateId>();
|
|
|
|
const auto core_id = hw::GetCurrentCoreId();
|
|
|
|
/* Validate arguments. */
|
|
SMC_R_UNLESS(state_type == PowerStateType_PowerDown, PsciDenied);
|
|
SMC_R_UNLESS(state_id == PowerStateId_Sc7, PsciDenied);
|
|
|
|
/* Orchestrate charger transition to Hi-Z mode if needed. */
|
|
if (IsChargerHiZModeEnabled()) {
|
|
/* Ensure we can do comms over i2c-1. */
|
|
clkrst::EnableI2c1Clock();
|
|
|
|
/* If the charger isn't in hi-z mode, perform a transition. */
|
|
if (!charger::IsHiZMode()) {
|
|
charger::EnterHiZMode();
|
|
|
|
/* Wait up to 50ms for the transition to complete. */
|
|
const auto start_time = util::GetMicroSeconds();
|
|
auto current_time = start_time;
|
|
while ((current_time - start_time) <= 50'000) {
|
|
if (auto intr_status = reg::Read(GPIO + 0x634); (intr_status & 1) == 0) {
|
|
/* Wait 256 us to ensure the transition completes. */
|
|
util::WaitMicroSeconds(256);
|
|
break;
|
|
}
|
|
current_time = util::GetMicroSeconds();
|
|
}
|
|
}
|
|
|
|
/* Disable i2c-1, since we're done communicating over it. */
|
|
clkrst::DisableI2c1Clock();
|
|
}
|
|
|
|
/* Enable wake event detection. */
|
|
pmc::EnableWakeEventDetection();
|
|
|
|
/* Ensure that i2c-5 is usable for communicating with the pmic. */
|
|
clkrst::EnableI2c5Clock();
|
|
i2c::Initialize(i2c::Port_5);
|
|
|
|
/* Orchestrate sleep entry with the pmic. */
|
|
pmic::EnableSleep();
|
|
|
|
/* Ensure that the soc is in a state valid for us to suspend. */
|
|
if (GetTargetFirmware() >= TargetFirmware_2_0_0) {
|
|
ValidateSocStateForSuspend();
|
|
}
|
|
|
|
/* Configure the pmc for sc7 entry. */
|
|
pmc::ConfigureForSc7Entry();
|
|
|
|
/* Configure the flow controller for sc7 entry. */
|
|
flow::SetCc4Ctrl(core_id, 0);
|
|
flow::SetHaltCpuEvents(core_id, false);
|
|
flow::ClearL2FlushControl();
|
|
flow::SetCpuCsr(core_id, FLOW_CTLR_CPUN_CSR_ENABLE_EXT_POWERGATE_CPU_TURNOFF_CPURAIL);
|
|
|
|
/* Save the entry context. */
|
|
SetEntryContext(core_id, entry_point, context_id);
|
|
|
|
/* Configure the cpu context for reset. */
|
|
SaveDebugRegisters();
|
|
SetCoreOff();
|
|
SetResetExpected(true);
|
|
|
|
/* Switch to use the common smc stack (all other cores are off), and perform suspension. */
|
|
PivotStackAndInvoke(reinterpret_cast<void *>(CommonSmcStackTop), SaveSecureContextAndSuspend);
|
|
|
|
/* This code will never be reached. */
|
|
__builtin_unreachable();
|
|
}
|
|
|
|
}
|
|
|
|
SmcResult SmcPowerOffCpu(SmcArguments &args) {
|
|
/* Get the current core id. */
|
|
const auto core_id = hw::GetCurrentCoreId();
|
|
|
|
/* Note that we're expecting a reset for the current core. */
|
|
SetResetExpected(true);
|
|
|
|
/* If we're on the final core, shut down directly. Otherwise, invoke with special stack. */
|
|
if (core_id == NumCores - 1) {
|
|
PowerOffCpu();
|
|
} else {
|
|
PivotStackAndInvoke(GetCoreExceptionStackVirtual(), PowerOffCpu);
|
|
}
|
|
|
|
/* This code will never be reached. */
|
|
__builtin_unreachable();
|
|
}
|
|
|
|
SmcResult SmcPowerOnCpu(SmcArguments &args) {
|
|
/* Get and validate the core to power on. */
|
|
const int which_core = args.r[1];
|
|
SMC_R_UNLESS(0 <= which_core && which_core < NumCores, PsciInvalidParameters);
|
|
|
|
/* Ensure the core isn't already on. */
|
|
SMC_R_UNLESS(!IsCoreOn(which_core), PsciAlreadyOn);
|
|
|
|
/* Save the entry context. */
|
|
SetEntryContext(which_core, args.r[2], args.r[3]);
|
|
|
|
/* Reset the cpu. */
|
|
ResetCpu(which_core);
|
|
|
|
/* Turn on the core. */
|
|
PowerOnCpu(CpuPowerGateStatusMasks[which_core], CpuPowerGateTogglePartitionIds[which_core]);
|
|
|
|
/* Start the core. */
|
|
StartCpu(which_core);
|
|
|
|
return SmcResult::PsciSuccess;
|
|
}
|
|
|
|
SmcResult SmcSuspendCpu(SmcArguments &args) {
|
|
return LockSecurityEngineAndInvoke(args, SuspendCpuImpl);
|
|
}
|
|
|
|
bool IsChargerHiZModeEnabled() {
|
|
return g_charger_hi_z_mode_enabled;
|
|
}
|
|
|
|
void SetChargerHiZModeEnabled(bool en) {
|
|
g_charger_hi_z_mode_enabled = en;
|
|
}
|
|
|
|
}
|