mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
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115 lines
4.2 KiB
C++
115 lines
4.2 KiB
C++
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <exosphere.hpp>
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namespace ams::clkrst {
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namespace {
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constinit uintptr_t g_register_address = secmon::MemoryRegionPhysicalDeviceClkRst.GetAddress();
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struct ClockParameters {
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uintptr_t reset_offset;
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uintptr_t clk_enb_offset;
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uintptr_t clk_src_offset;
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u8 index;
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u8 clk_src;
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u8 clk_div;
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};
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void EnableClock(const ClockParameters ¶m) {
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/* Hold reset. */
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reg::ReadWrite(g_register_address + param.reset_offset, REG_BITS_VALUE(param.index, 1, 1));
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/* Disable clock. */
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reg::ReadWrite(g_register_address + param.clk_enb_offset, REG_BITS_VALUE(param.index, 1, 0));
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/* Set the clock source. */
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if (param.clk_src_offset != 0) {
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reg::Write(g_register_address + param.clk_src_offset, (param.clk_src << 29) | (param.clk_div << 0));
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}
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/* Enable clk. */
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reg::ReadWrite(g_register_address + param.clk_enb_offset, REG_BITS_VALUE(param.index, 1, 1));
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/* Release reset. */
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reg::ReadWrite(g_register_address + param.reset_offset, REG_BITS_VALUE(param.index, 1, 0));
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}
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void DisableClock(const ClockParameters ¶m) {
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/* Hold reset. */
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reg::ReadWrite(g_register_address + param.reset_offset, REG_BITS_VALUE(param.index, 1, 1));
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/* Disable clock. */
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reg::ReadWrite(g_register_address + param.clk_enb_offset, REG_BITS_VALUE(param.index, 1, 0));
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}
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#define DEFINE_CLOCK_PARAMETERS(_VARNAME_, _REG_, _NAME_, _CLK_, _DIV_) \
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constexpr inline const ClockParameters _VARNAME_ = { \
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.reset_offset = CLK_RST_CONTROLLER_RST_DEVICES_##_REG_, \
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.clk_enb_offset = CLK_RST_CONTROLLER_CLK_OUT_ENB_##_REG_, \
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.clk_src_offset = CLK_RST_CONTROLLER_CLK_SOURCE_##_NAME_, \
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.index = CLK_RST_CONTROLLER_CLK_ENB_##_NAME_##_INDEX, \
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.clk_src = CLK_RST_CONTROLLER_CLK_SOURCE_##_NAME_##_##_NAME_##_CLK_SRC_##_CLK_, \
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.clk_div = _DIV_, \
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}
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DEFINE_CLOCK_PARAMETERS(UartAClock, L, UARTA, PLLP_OUT0, 0);
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DEFINE_CLOCK_PARAMETERS(UartBClock, L, UARTB, PLLP_OUT0, 0);
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DEFINE_CLOCK_PARAMETERS(UartCClock, H, UARTC, PLLP_OUT0, 0);
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DEFINE_CLOCK_PARAMETERS(I2c1Clock, L, I2C1, CLK_M, 0);
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DEFINE_CLOCK_PARAMETERS(I2c5Clock, H, I2C5, CLK_M, 0);
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DEFINE_CLOCK_PARAMETERS(ActmonClock, V, ACTMON, CLK_M, 0);
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}
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void SetRegisterAddress(uintptr_t address) {
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g_register_address = address;
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}
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void SetFuseVisibility(bool visible) {
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reg::ReadWrite(g_register_address + CLK_RST_CONTROLLER_MISC_CLK_ENB, CLK_RST_REG_BITS_VALUE(MISC_CLK_ENB_CFG_ALL_VISIBLE, visible ? 1 : 0));
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}
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void EnableUartAClock() {
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EnableClock(UartAClock);
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}
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void EnableUartBClock() {
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EnableClock(UartBClock);
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}
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void EnableUartCClock() {
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EnableClock(UartCClock);
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}
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void EnableActmonClock() {
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EnableClock(ActmonClock);
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}
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void EnableI2c1Clock() {
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EnableClock(I2c1Clock);
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}
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void EnableI2c5Clock() {
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EnableClock(I2c5Clock);
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}
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void DisableI2c1Clock() {
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DisableClock(I2c1Clock);
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}
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}
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