mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-11-18 01:46:47 +00:00
333 lines
15 KiB
C++
333 lines
15 KiB
C++
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <exosphere.hpp>
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#include "../fusee_fatal.hpp"
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#include "../fusee_uncompress.hpp"
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#include "fusee_mtc.hpp"
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#include "fusee_mtc_timing_table_mariko.hpp"
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namespace ams::nxboot {
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namespace {
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constexpr inline const uintptr_t CLKRST = secmon::MemoryRegionPhysicalDeviceClkRst.GetAddress();
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constexpr inline const uintptr_t MC = MC_BASE;
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constexpr inline const uintptr_t EMC = EMC_BASE;
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constexpr inline const uintptr_t EMC0 = EMC0_BASE;
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constexpr inline const uintptr_t EMC1 = EMC1_BASE;
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static constinit bool g_next_pll = false;
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static constinit bool g_did_first_training = false;
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static constinit bool g_fsp_for_next_freq = false;
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#include "fusee_mtc_tables_mariko.inc"
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#define DECLARE_OFFSET_HANDLER(BASE, REG, NAME) REG,
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#define DECLARE_REGISTER_HANDLER(BASE, REG, NAME) BASE + REG,
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constexpr inline const u16 BurstRegistersOffsets[] = {
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FOREACH_BURST_REG(DECLARE_OFFSET_HANDLER)
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};
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constexpr inline const u32 TrimRegisters[] = {
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FOREACH_TRIM_REG(DECLARE_REGISTER_HANDLER)
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};
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constexpr inline const u32 BurstMcRegisters[] = {
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FOREACH_BURST_MC_REG(DECLARE_REGISTER_HANDLER)
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};
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constexpr inline const u32 LaScaleRegisters[] = {
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FOREACH_LA_SCALE_REG(DECLARE_REGISTER_HANDLER)
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};
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constexpr inline const u32 PerChannelTrimRegisters[] = {
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FOREACH_PER_CHANNEL_TRIM_REG(DECLARE_REGISTER_HANDLER)
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};
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constexpr inline const u32 PerChannelBurstRegisters[] = {
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FOREACH_PER_CHANNEL_BURST_REG(DECLARE_REGISTER_HANDLER)
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};
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constexpr inline const u32 PerChannelVrefRegisters[] = {
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FOREACH_PER_CHANNEL_VREF_REG(DECLARE_REGISTER_HANDLER)
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};
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constexpr inline const u32 PerChannelTrainingModRegisters[] = {
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FOREACH_PER_CHANNEL_TRAINING_MOD_REG(DECLARE_REGISTER_HANDLER)
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};
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using EmcDvfsTimingTable = mariko::EmcDvfsTimingTable;
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EmcDvfsTimingTable *GetEmcDvfsTimingTables(int index, void *mtc_tables_buffer) {
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/* Get the compressed table. */
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u8 *cmp_table;
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size_t cmp_table_size;
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switch (index) {
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#define HANDLE_CASE(N, TABLE) \
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case N: \
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cmp_table = TABLE; \
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cmp_table_size = sizeof(TABLE); \
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break;
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HANDLE_CASE(0x00, T210b01SdevEmcDvfsTableS4gb01)
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HANDLE_CASE(0x05, T210b01SdevEmcDvfsTableS4gb03)
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HANDLE_CASE(0x06, T210b01SdevEmcDvfsTableS8gb03)
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HANDLE_CASE(0x07, T210b01SdevEmcDvfsTableH4gb03)
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HANDLE_CASE(0x08, T210b01SdevEmcDvfsTableM4gb03)
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HANDLE_CASE(0x09, T210b01SdevEmcDvfsTableS4gbY01)
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HANDLE_CASE(0x0A, T210b01SdevEmcDvfsTableS1y4gbY01)
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HANDLE_CASE(0x0B, T210b01SdevEmcDvfsTableS1y8gbY01)
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HANDLE_CASE(0x0C, T210b01SdevEmcDvfsTableS1y4gbX03)
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HANDLE_CASE(0x0D, T210b01SdevEmcDvfsTableS1y8gbX03)
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HANDLE_CASE(0x0E, T210b01SdevEmcDvfsTableS1y4gb01)
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HANDLE_CASE(0x0F, T210b01SdevEmcDvfsTableM1y4gb01)
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HANDLE_CASE(0x10, T210b01SdevEmcDvfsTableH1y4gb01)
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default:
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ShowFatalError("Unknown EmcDvfsTimingTableIndex: %d\n", index);
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}
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/* Uncompress the table. */
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EmcDvfsTimingTable *out_tables = reinterpret_cast<EmcDvfsTimingTable *>(mtc_tables_buffer);
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Uncompress(out_tables, 2 * sizeof(EmcDvfsTimingTable), cmp_table, cmp_table_size);
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return out_tables;
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}
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bool IsSamePll(u32 next_2x, u32 prev_2x) {
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if (next_2x == prev_2x) {
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return true;
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} else if ((next_2x == PLLM_OUT0 || next_2x == PLLM_UD) && (prev_2x == PLLM_OUT0 || prev_2x == PLLM_UD)) {
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return true;
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} else {
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return false;
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}
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}
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bool PllReprogram(u32 next_rate_khz, u32 next_clk_src, u32 prev_rate_khz, u32 prev_clk_src) {
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/* Get current divp value. */
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u32 pll_p;
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switch (reg::GetValue(CLKRST + CLK_RST_CONTROLLER_CLK_SOURCE_EMC, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC))) {
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case PLLM_UD:
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case PLLM_OUT0:
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pll_p = reg::GetValue(CLKRST + CLK_RST_CONTROLLER_PLLM_BASE, CLK_RST_REG_BITS_MASK(PLLM_BASE_PLLM_DIVP_B01));
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break;
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case PLLMB_UD:
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case PLLMB_OUT0:
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pll_p = reg::GetValue(CLKRST + CLK_RST_CONTROLLER_PLLMB_BASE, CLK_RST_REG_BITS_MASK(PLLMB_BASE_PLLMB_DIVP_B01));
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break;
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default:
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pll_p = 0;
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break;
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}
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/* Get clk src/divisor. */
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const u32 next_2x = reg::GetField(next_clk_src, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC));
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const u32 prev_2x = reg::GetField(prev_clk_src, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC));
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u32 next_div = reg::GetField(next_clk_src, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR));
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u32 prev_div = reg::GetField(prev_clk_src, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR));
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/* Update divisor, if necessary. */
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if (next_2x == PLLM_UD || next_2x == PLLMB_UD) {
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next_div = 0;
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}
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if (prev_2x == PLLM_UD || prev_2x == PLLMB_UD) {
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prev_div = 0;
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}
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/* If the pll is different, reprogramming is necessary. */
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if (!IsSamePll(next_2x, prev_2x)) {
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return true;
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}
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/* Return whether the ratios are different. */
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const float next_freq = next_rate_khz * (1 + (next_div >> 1) + (0.5 * (next_div & 1))) * (pll_p + 1);
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const float prev_freq = prev_rate_khz * (1 + (prev_div >> 1) + (0.5 * (prev_div & 1))) * (pll_p + 1);
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const float ratio = prev_freq / next_freq;
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return ratio > 1.01 || ratio < 0.99;
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}
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u32 ProgramPllm(u32 next_rate_khz, u32 next_clk_src, u32 ret_clk_src, bool is_pllmb, EmcDvfsTimingTable *timing_tables) {
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u32 ret = ret_clk_src;
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const uint32_t base = ((timing_tables->pllmb_divm & 0xFF) | ((timing_tables->pllmb_divn & 0xFF) << 8) | ((timing_tables->pllmb_divp & 1) << 20));
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if (is_pllmb) {
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reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLMB_BASE, base);
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reg::Read(CLKRST + CLK_RST_CONTROLLER_PLLMB_BASE);
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reg::SetBits(CLKRST + CLK_RST_CONTROLLER_PLLMB_MISC1, 0x10000000);
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if (timing_tables->pll_en_ssc & 1) {
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reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLMB_SS_CFG, timing_tables->pllmb_ss_cfg);
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reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLMB_SS_CTRL1, timing_tables->pllmb_ss_ctrl1);
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reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLMB_SS_CTRL2, timing_tables->pllmb_ss_ctrl2);
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} else {
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reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLMB_SS_CFG, timing_tables->pllmb_ss_cfg & 0xBFFFFFFF);
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reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLMB_SS_CTRL2, timing_tables->pllmb_ss_ctrl2 & 0x0000FFFF);
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}
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reg::SetBits(CLKRST + CLK_RST_CONTROLLER_PLLMB_BASE, 0x40000000);
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switch (reg::GetField(ret, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC))) {
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case PLLM_OUT0:
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reg::SetField(ret, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, PLLMB_OUT0));
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break;
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case PLLM_UD:
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reg::SetField(ret, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, PLLMB_UD));
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break;
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}
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while ((reg::Read(CLKRST + CLK_RST_CONTROLLER_PLLMB_BASE) & 0x8000000) == 0) { /* ... */ }
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return ret;
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} else {
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reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLM_BASE, base);
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reg::Read(CLKRST + CLK_RST_CONTROLLER_PLLM_BASE);
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reg::SetBits(CLKRST + CLK_RST_CONTROLLER_PLLM_MISC2, 0x10);
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if (timing_tables->pll_en_ssc & 1) {
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reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLM_SS_CFG, timing_tables->pllm_ss_cfg);
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reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLM_SS_CTRL1, timing_tables->pllm_ss_ctrl1);
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reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLM_SS_CTRL2, timing_tables->pllm_ss_ctrl2);
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} else {
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reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLM_SS_CFG, timing_tables->pllm_ss_cfg & 0xBFFFFFFF);
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reg::Write(CLKRST + CLK_RST_CONTROLLER_PLLM_SS_CTRL2, timing_tables->pllm_ss_ctrl2 & 0x0000FFFF);
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}
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reg::SetBits(CLKRST + CLK_RST_CONTROLLER_PLLM_BASE, 0x40000000);
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switch (reg::GetField(ret, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC))) {
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case PLLM_OUT0:
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reg::SetField(ret, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, PLLM_OUT0));
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break;
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case PLLM_UD:
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reg::SetField(ret, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, PLLM_UD));
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break;
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}
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while ((reg::Read(CLKRST + CLK_RST_CONTROLLER_PLLM_BASE) & 0x8000000) == 0) { /* ... */ }
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return ret;
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}
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}
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void FreqChange(EmcDvfsTimingTable *src_timing, EmcDvfsTimingTable *dst_timing, u32 training, u32 next_clk_src) {
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/* TODO */
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}
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void TrainFreq(EmcDvfsTimingTable *src_timing, EmcDvfsTimingTable *dst_timing, u32 next_clk_src) {
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/* TODO */
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}
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void Dvfs(EmcDvfsTimingTable *dst_timing, EmcDvfsTimingTable *src_timing, bool train) {
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/* Get the clock sources/rates. */
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u32 clk_src_emc_from = src_timing->clk_src_emc;
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u32 clk_src_emc_to = dst_timing->clk_src_emc;
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u32 rate_from = src_timing->rate_khz;
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u32 rate_to = dst_timing->rate_khz;
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/* Get channel enables. */
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const bool ch0_enable = reg::GetField(dst_timing->emc_fbio_cfg7, EMC_REG_BITS_MASK(FBIO_CFG7_CH0_ENABLE)) == EMC_FBIO_CFG7_CH0_ENABLE_ENABLE;
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const bool ch1_enable = reg::GetField(dst_timing->emc_fbio_cfg7, EMC_REG_BITS_MASK(FBIO_CFG7_CH1_ENABLE)) == EMC_FBIO_CFG7_CH1_ENABLE_ENABLE;
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/* Reprogram pll. */
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const u32 prev_2x_clk_src = reg::GetField(clk_src_emc_from, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC));
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const u32 next_2x_clk_src = reg::GetField(clk_src_emc_to, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC));
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if (next_2x_clk_src != PLLP_OUT0 && next_2x_clk_src != PLLP_UD) {
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if (ch0_enable || ch1_enable) {
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if (PllReprogram(rate_to, clk_src_emc_to, rate_from, clk_src_emc_from)) {
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if (prev_2x_clk_src == PLLMB_UD || prev_2x_clk_src == PLLMB_OUT0) {
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g_next_pll = 0;
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} else if (prev_2x_clk_src == PLLM_UD || prev_2x_clk_src == PLLM_OUT0) {
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g_next_pll = !g_next_pll;
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}
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clk_src_emc_to = ProgramPllm(rate_to, clk_src_emc_to, clk_src_emc_to, g_next_pll, dst_timing);
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} else {
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if (next_2x_clk_src == PLLM_UD || next_2x_clk_src == PLLMB_UD) {
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if (g_next_pll) {
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reg::SetField(clk_src_emc_to, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, PLLMB_UD));
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}
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} else if (next_2x_clk_src == PLLM_OUT0 || next_2x_clk_src == PLLMB_OUT0) {
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if (g_next_pll) {
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reg::SetField(clk_src_emc_to, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, PLLMB_OUT0));
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}
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}
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}
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}
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}
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if (train) {
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TrainFreq(src_timing, dst_timing, clk_src_emc_to);
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if (ch0_enable || ch1_enable) {
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if (PllReprogram(dst_timing->rate_khz, dst_timing->clk_src_emc, src_timing->rate_khz, src_timing->clk_src_emc)) {
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g_next_pll = !g_next_pll;
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}
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}
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} else {
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FreqChange(src_timing, dst_timing, 0, clk_src_emc_to);
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}
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}
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}
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void DoMemoryTrainingMariko(bool *out_did_training, int index, void *mtc_tables_buffer) {
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/* Get timing tables. */
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auto *timing_tables = GetEmcDvfsTimingTables(index, mtc_tables_buffer);
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auto *src_timing = timing_tables + 0;
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auto *dst_timing = timing_tables + 1;
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/* Check timing tables. */
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if (src_timing->rate_khz != 204000 || dst_timing->rate_khz != 1600000) {
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ShowFatalError("EmcDvfsTimingTables seem corrupted %" PRIu32 " %" PRIu32 "?\n", src_timing->rate_khz, dst_timing->rate_khz);
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}
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/* Check that we should do training. */
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if (src_timing->clk_src_emc != reg::Read(CLKRST + CLK_RST_CONTROLLER_CLK_SOURCE_EMC)) {
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/* Our clock source isn't what's expected, so presumably training has already been done? */
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/* Either way, the safe bet is to skip it. */
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*out_did_training = false;
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return;
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}
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/* Train 1600MHz. */
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Dvfs(dst_timing, src_timing, true);
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/* Switch to 1600MHz. */
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Dvfs(dst_timing, src_timing, false);
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/* Set ourselves as having done training */
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*out_did_training = true;
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}
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void RestoreMemoryClockRateMariko(void *mtc_tables_buffer) {
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/* Get timing tables. */
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auto *timing_tables = reinterpret_cast<EmcDvfsTimingTable *>(mtc_tables_buffer);
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auto *src_timing = timing_tables + 0;
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auto *dst_timing = timing_tables + 1;
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/* Check timing tables. */
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if (src_timing->rate_khz != 204000 || dst_timing->rate_khz != 1600000) {
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ShowFatalError("EmcDvfsTimingTables seem corrupted %" PRIu32 " %" PRIu32 "?\n", src_timing->rate_khz, dst_timing->rate_khz);
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}
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/* Switch to 204MHz */
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Dvfs(src_timing, dst_timing, false);
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}
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}
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