mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-11-27 06:12:15 +00:00
484 lines
17 KiB
C
484 lines
17 KiB
C
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef FUSEE_FUSE_H
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#define FUSEE_FUSE_H
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#define FUSE_BASE 0x7000F800
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#define FUSE_CHIP_BASE (FUSE_BASE + 0x98)
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#define MAKE_FUSE_REG(n) MAKE_REG32(FUSE_BASE + n)
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#define MAKE_FUSE_CHIP_REG(n) MAKE_REG32(FUSE_CHIP_BASE + n)
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typedef struct {
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uint32_t FUSE_FUSECTRL;
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uint32_t FUSE_FUSEADDR;
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uint32_t FUSE_FUSERDATA;
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uint32_t FUSE_FUSEWDATA;
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uint32_t FUSE_FUSETIME_RD1;
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uint32_t FUSE_FUSETIME_RD2;
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uint32_t FUSE_FUSETIME_PGM1;
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uint32_t FUSE_FUSETIME_PGM2;
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uint32_t FUSE_PRIV2INTFC_START;
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uint32_t FUSE_FUSEBYPASS;
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uint32_t FUSE_PRIVATEKEYDISABLE;
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uint32_t FUSE_DISABLEREGPROGRAM;
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uint32_t FUSE_WRITE_ACCESS_SW;
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uint32_t FUSE_PWR_GOOD_SW;
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uint32_t _0x38;
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uint32_t FUSE_PRIV2RESHIFT;
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uint32_t _0x40[0x3];
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uint32_t FUSE_FUSETIME_RD3;
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uint32_t _0x50[0xC];
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uint32_t FUSE_PRIVATE_KEY0_NONZERO;
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uint32_t FUSE_PRIVATE_KEY1_NONZERO;
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uint32_t FUSE_PRIVATE_KEY2_NONZERO;
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uint32_t FUSE_PRIVATE_KEY3_NONZERO;
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uint32_t FUSE_PRIVATE_KEY4_NONZERO;
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uint32_t _0x94;
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} tegra_fuse_t;
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typedef struct {
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uint32_t _0x98[0x1A];
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uint32_t FUSE_PRODUCTION_MODE;
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uint32_t FUSE_JTAG_SECUREID_VALID;
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uint32_t FUSE_ODM_LOCK;
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uint32_t FUSE_OPT_OPENGL_EN;
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uint32_t FUSE_SKU_INFO;
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uint32_t FUSE_CPU_SPEEDO_0_CALIB;
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uint32_t FUSE_CPU_IDDQ_CALIB;
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uint32_t _0x11C[0x3];
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uint32_t FUSE_OPT_FT_REV;
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uint32_t FUSE_CPU_SPEEDO_1_CALIB;
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uint32_t FUSE_CPU_SPEEDO_2_CALIB;
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uint32_t FUSE_SOC_SPEEDO_0_CALIB;
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uint32_t FUSE_SOC_SPEEDO_1_CALIB;
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uint32_t FUSE_SOC_SPEEDO_2_CALIB;
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uint32_t FUSE_SOC_IDDQ_CALIB;
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uint32_t _0x144;
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uint32_t FUSE_FA;
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uint32_t FUSE_RESERVED_PRODUCTION;
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uint32_t FUSE_HDMI_LANE0_CALIB;
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uint32_t FUSE_HDMI_LANE1_CALIB;
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uint32_t FUSE_HDMI_LANE2_CALIB;
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uint32_t FUSE_HDMI_LANE3_CALIB;
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uint32_t FUSE_ENCRYPTION_RATE;
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uint32_t FUSE_PUBLIC_KEY[0x8];
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uint32_t FUSE_TSENSOR1_CALIB;
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uint32_t FUSE_TSENSOR2_CALIB;
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uint32_t _0x18C;
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uint32_t FUSE_OPT_CP_REV;
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uint32_t FUSE_OPT_PFG;
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uint32_t FUSE_TSENSOR0_CALIB;
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uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE;
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uint32_t FUSE_SECURITY_MODE;
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uint32_t FUSE_PRIVATE_KEY[0x5];
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uint32_t FUSE_ARM_JTAG_DIS;
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uint32_t FUSE_BOOT_DEVICE_INFO;
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uint32_t FUSE_RESERVED_SW;
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uint32_t FUSE_OPT_VP9_DISABLE;
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uint32_t FUSE_RESERVED_ODM0[0x8];
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uint32_t FUSE_OBS_DIS;
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uint32_t _0x1EC;
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uint32_t FUSE_USB_CALIB;
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uint32_t FUSE_SKU_DIRECT_CONFIG;
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uint32_t FUSE_KFUSE_PRIVKEY_CTRL;
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uint32_t FUSE_PACKAGE_INFO;
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uint32_t FUSE_OPT_VENDOR_CODE;
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uint32_t FUSE_OPT_FAB_CODE;
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uint32_t FUSE_OPT_LOT_CODE_0;
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uint32_t FUSE_OPT_LOT_CODE_1;
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uint32_t FUSE_OPT_WAFER_ID;
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uint32_t FUSE_OPT_X_COORDINATE;
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uint32_t FUSE_OPT_Y_COORDINATE;
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uint32_t FUSE_OPT_SEC_DEBUG_EN;
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uint32_t FUSE_OPT_OPS_RESERVED;
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uint32_t _0x224;
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uint32_t FUSE_GPU_IDDQ_CALIB;
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uint32_t FUSE_TSENSOR3_CALIB;
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uint32_t FUSE_CLOCK_BOUNDOUT0;
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uint32_t FUSE_CLOCK_BOUNDOUT1;
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uint32_t _0x238[0x3];
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uint32_t FUSE_OPT_SAMPLE_TYPE;
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uint32_t FUSE_OPT_SUBREVISION;
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uint32_t FUSE_OPT_SW_RESERVED_0;
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uint32_t FUSE_OPT_SW_RESERVED_1;
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uint32_t FUSE_TSENSOR4_CALIB;
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uint32_t FUSE_TSENSOR5_CALIB;
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uint32_t FUSE_TSENSOR6_CALIB;
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uint32_t FUSE_TSENSOR7_CALIB;
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uint32_t FUSE_OPT_PRIV_SEC_EN;
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uint32_t _0x268[0x5];
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uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE;
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uint32_t FUSE_TSENSOR_COMMON;
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uint32_t FUSE_OPT_CP_BIN;
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uint32_t FUSE_OPT_GPU_DISABLE;
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uint32_t FUSE_OPT_FT_BIN;
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uint32_t FUSE_OPT_DONE_MAP;
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uint32_t _0x294;
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uint32_t FUSE_APB2JTAG_DISABLE;
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uint32_t FUSE_ODM_INFO;
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uint32_t _0x2A0[0x2];
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uint32_t FUSE_ARM_CRYPT_DE_FEATURE;
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uint32_t _0x2AC[0x5];
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uint32_t FUSE_WOA_SKU_FLAG;
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uint32_t FUSE_ECO_RESERVE_1;
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uint32_t FUSE_GCPLEX_CONFIG_FUSE;
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uint32_t FUSE_PRODUCTION_MONTH;
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uint32_t FUSE_RAM_REPAIR_INDICATOR;
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uint32_t FUSE_TSENSOR9_CALIB;
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uint32_t _0x2D8;
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uint32_t FUSE_VMIN_CALIBRATION;
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uint32_t FUSE_AGING_SENSOR_CALIBRATION;
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uint32_t FUSE_DEBUG_AUTHENTICATION;
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uint32_t FUSE_SECURE_PROVISION_INDEX;
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uint32_t FUSE_SECURE_PROVISION_INFO;
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uint32_t FUSE_OPT_GPU_DISABLE_CP1;
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uint32_t FUSE_SPARE_ENDIS;
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uint32_t FUSE_ECO_RESERVE_0;
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uint32_t _0x2FC[0x2];
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uint32_t FUSE_RESERVED_CALIB0;
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uint32_t FUSE_RESERVED_CALIB1;
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uint32_t FUSE_OPT_GPU_TPC0_DISABLE;
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uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1;
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uint32_t FUSE_OPT_CPU_DISABLE;
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uint32_t FUSE_OPT_CPU_DISABLE_CP1;
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uint32_t FUSE_TSENSOR10_CALIB;
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uint32_t FUSE_TSENSOR10_CALIB_AUX;
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uint32_t _0x324[0x5];
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uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2;
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uint32_t FUSE_OPT_GPU_TPC1_DISABLE;
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uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1;
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uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2;
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uint32_t FUSE_OPT_CPU_DISABLE_CP2;
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uint32_t FUSE_OPT_GPU_DISABLE_CP2;
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uint32_t FUSE_USB_CALIB_EXT;
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uint32_t FUSE_RESERVED_FIELD;
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uint32_t _0x358[0x9];
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uint32_t FUSE_SPARE_REALIGNMENT_REG;
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uint32_t FUSE_SPARE_BIT[0x20];
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} tegra_fuse_chip_common_t;
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typedef struct {
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uint32_t _0x98[0x1A];
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uint32_t FUSE_PRODUCTION_MODE;
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uint32_t FUSE_JTAG_SECUREID_VALID;
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uint32_t FUSE_ODM_LOCK;
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uint32_t FUSE_OPT_OPENGL_EN;
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uint32_t FUSE_SKU_INFO;
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uint32_t FUSE_CPU_SPEEDO_0_CALIB;
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uint32_t FUSE_CPU_IDDQ_CALIB;
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uint32_t _0x11C[0x3];
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uint32_t FUSE_OPT_FT_REV;
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uint32_t FUSE_CPU_SPEEDO_1_CALIB;
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uint32_t FUSE_CPU_SPEEDO_2_CALIB;
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uint32_t FUSE_SOC_SPEEDO_0_CALIB;
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uint32_t FUSE_SOC_SPEEDO_1_CALIB;
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uint32_t FUSE_SOC_SPEEDO_2_CALIB;
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uint32_t FUSE_SOC_IDDQ_CALIB;
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uint32_t _0x144;
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uint32_t FUSE_FA;
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uint32_t FUSE_RESERVED_PRODUCTION;
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uint32_t FUSE_HDMI_LANE0_CALIB;
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uint32_t FUSE_HDMI_LANE1_CALIB;
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uint32_t FUSE_HDMI_LANE2_CALIB;
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uint32_t FUSE_HDMI_LANE3_CALIB;
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uint32_t FUSE_ENCRYPTION_RATE;
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uint32_t FUSE_PUBLIC_KEY[0x8];
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uint32_t FUSE_TSENSOR1_CALIB;
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uint32_t FUSE_TSENSOR2_CALIB;
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uint32_t _0x18C;
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uint32_t FUSE_OPT_CP_REV;
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uint32_t FUSE_OPT_PFG;
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uint32_t FUSE_TSENSOR0_CALIB;
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uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE;
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uint32_t FUSE_SECURITY_MODE;
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uint32_t FUSE_PRIVATE_KEY[0x5];
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uint32_t FUSE_ARM_JTAG_DIS;
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uint32_t FUSE_BOOT_DEVICE_INFO;
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uint32_t FUSE_RESERVED_SW;
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uint32_t FUSE_OPT_VP9_DISABLE;
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uint32_t FUSE_RESERVED_ODM0[0x8];
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uint32_t FUSE_OBS_DIS;
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uint32_t _0x1EC;
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uint32_t FUSE_USB_CALIB;
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uint32_t FUSE_SKU_DIRECT_CONFIG;
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uint32_t FUSE_KFUSE_PRIVKEY_CTRL;
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uint32_t FUSE_PACKAGE_INFO;
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uint32_t FUSE_OPT_VENDOR_CODE;
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uint32_t FUSE_OPT_FAB_CODE;
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uint32_t FUSE_OPT_LOT_CODE_0;
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uint32_t FUSE_OPT_LOT_CODE_1;
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uint32_t FUSE_OPT_WAFER_ID;
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uint32_t FUSE_OPT_X_COORDINATE;
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uint32_t FUSE_OPT_Y_COORDINATE;
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uint32_t FUSE_OPT_SEC_DEBUG_EN;
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uint32_t FUSE_OPT_OPS_RESERVED;
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uint32_t FUSE_SATA_CALIB; /* Erista only. */
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uint32_t FUSE_GPU_IDDQ_CALIB;
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uint32_t FUSE_TSENSOR3_CALIB;
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uint32_t FUSE_CLOCK_BOUNDOUT0;
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uint32_t FUSE_CLOCK_BOUNDOUT1;
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uint32_t _0x238[0x3];
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uint32_t FUSE_OPT_SAMPLE_TYPE;
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uint32_t FUSE_OPT_SUBREVISION;
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uint32_t FUSE_OPT_SW_RESERVED_0;
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uint32_t FUSE_OPT_SW_RESERVED_1;
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uint32_t FUSE_TSENSOR4_CALIB;
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uint32_t FUSE_TSENSOR5_CALIB;
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uint32_t FUSE_TSENSOR6_CALIB;
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uint32_t FUSE_TSENSOR7_CALIB;
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uint32_t FUSE_OPT_PRIV_SEC_EN;
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uint32_t FUSE_PKC_DISABLE; /* Erista only. */
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uint32_t _0x26C[0x4];
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uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE;
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uint32_t FUSE_TSENSOR_COMMON;
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uint32_t FUSE_OPT_CP_BIN;
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uint32_t FUSE_OPT_GPU_DISABLE;
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uint32_t FUSE_OPT_FT_BIN;
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uint32_t FUSE_OPT_DONE_MAP;
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uint32_t _0x294;
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uint32_t FUSE_APB2JTAG_DISABLE;
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uint32_t FUSE_ODM_INFO;
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uint32_t _0x2A0[0x2];
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uint32_t FUSE_ARM_CRYPT_DE_FEATURE;
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uint32_t _0x2AC[0x5];
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uint32_t FUSE_WOA_SKU_FLAG;
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uint32_t FUSE_ECO_RESERVE_1;
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uint32_t FUSE_GCPLEX_CONFIG_FUSE;
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uint32_t FUSE_PRODUCTION_MONTH;
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uint32_t FUSE_RAM_REPAIR_INDICATOR;
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uint32_t FUSE_TSENSOR9_CALIB;
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uint32_t _0x2D8;
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uint32_t FUSE_VMIN_CALIBRATION;
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uint32_t FUSE_AGING_SENSOR_CALIBRATION;
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uint32_t FUSE_DEBUG_AUTHENTICATION;
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uint32_t FUSE_SECURE_PROVISION_INDEX;
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uint32_t FUSE_SECURE_PROVISION_INFO;
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uint32_t FUSE_OPT_GPU_DISABLE_CP1;
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uint32_t FUSE_SPARE_ENDIS;
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uint32_t FUSE_ECO_RESERVE_0;
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uint32_t _0x2FC[0x2];
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uint32_t FUSE_RESERVED_CALIB0;
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uint32_t FUSE_RESERVED_CALIB1;
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uint32_t FUSE_OPT_GPU_TPC0_DISABLE;
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uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1;
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uint32_t FUSE_OPT_CPU_DISABLE;
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uint32_t FUSE_OPT_CPU_DISABLE_CP1;
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uint32_t FUSE_TSENSOR10_CALIB;
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uint32_t FUSE_TSENSOR10_CALIB_AUX;
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uint32_t FUSE_OPT_RAM_SVOP_DP; /* Erista only. */
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uint32_t FUSE_OPT_RAM_SVOP_PDP; /* Erista only. */
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uint32_t FUSE_OPT_RAM_SVOP_REG; /* Erista only. */
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uint32_t FUSE_OPT_RAM_SVOP_SP; /* Erista only. */
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uint32_t FUSE_OPT_RAM_SVOP_SMPDP; /* Erista only. */
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uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2;
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uint32_t FUSE_OPT_GPU_TPC1_DISABLE;
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uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1;
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uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2;
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uint32_t FUSE_OPT_CPU_DISABLE_CP2;
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uint32_t FUSE_OPT_GPU_DISABLE_CP2;
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uint32_t FUSE_USB_CALIB_EXT;
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uint32_t FUSE_RESERVED_FIELD;
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uint32_t _0x358[0x9];
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uint32_t FUSE_SPARE_REALIGNMENT_REG;
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uint32_t FUSE_SPARE_BIT[0x20];
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} tegra_fuse_chip_erista_t;
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typedef struct {
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uint32_t FUSE_RESERVED_ODM8[0xE]; /* Mariko only. */
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uint32_t FUSE_KEK[0x4]; /* Mariko only. */
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uint32_t FUSE_BEK[0x4]; /* Mariko only. */
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uint32_t _0xF0; /* Mariko only. */
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uint32_t _0xF4; /* Mariko only. */
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uint32_t _0xF8; /* Mariko only. */
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uint32_t _0xFC; /* Mariko only. */
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uint32_t FUSE_PRODUCTION_MODE;
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uint32_t FUSE_JTAG_SECUREID_VALID;
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uint32_t FUSE_ODM_LOCK;
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uint32_t FUSE_OPT_OPENGL_EN;
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uint32_t FUSE_SKU_INFO;
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uint32_t FUSE_CPU_SPEEDO_0_CALIB;
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uint32_t FUSE_CPU_IDDQ_CALIB;
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uint32_t FUSE_RESERVED_ODM22[0x3]; /* Mariko only. */
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uint32_t FUSE_OPT_FT_REV;
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uint32_t FUSE_CPU_SPEEDO_1_CALIB;
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uint32_t FUSE_CPU_SPEEDO_2_CALIB;
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uint32_t FUSE_SOC_SPEEDO_0_CALIB;
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uint32_t FUSE_SOC_SPEEDO_1_CALIB;
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uint32_t FUSE_SOC_SPEEDO_2_CALIB;
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uint32_t FUSE_SOC_IDDQ_CALIB;
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uint32_t FUSE_RESERVED_ODM25; /* Mariko only. */
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uint32_t FUSE_FA;
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uint32_t FUSE_RESERVED_PRODUCTION;
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uint32_t FUSE_HDMI_LANE0_CALIB;
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uint32_t FUSE_HDMI_LANE1_CALIB;
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uint32_t FUSE_HDMI_LANE2_CALIB;
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uint32_t FUSE_HDMI_LANE3_CALIB;
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uint32_t FUSE_ENCRYPTION_RATE;
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uint32_t FUSE_PUBLIC_KEY[0x8];
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uint32_t FUSE_TSENSOR1_CALIB;
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uint32_t FUSE_TSENSOR2_CALIB;
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uint32_t FUSE_OPT_SECURE_SCC_DIS; /* Mariko only. */
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uint32_t FUSE_OPT_CP_REV;
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uint32_t FUSE_OPT_PFG;
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uint32_t FUSE_TSENSOR0_CALIB;
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uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE;
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uint32_t FUSE_SECURITY_MODE;
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uint32_t FUSE_PRIVATE_KEY[0x5];
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uint32_t FUSE_ARM_JTAG_DIS;
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uint32_t FUSE_BOOT_DEVICE_INFO;
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uint32_t FUSE_RESERVED_SW;
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uint32_t FUSE_OPT_VP9_DISABLE;
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uint32_t FUSE_RESERVED_ODM0[0x8];
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uint32_t FUSE_OBS_DIS;
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uint32_t _0x1EC; /* Mariko only. */
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uint32_t FUSE_USB_CALIB;
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uint32_t FUSE_SKU_DIRECT_CONFIG;
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uint32_t FUSE_KFUSE_PRIVKEY_CTRL;
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uint32_t FUSE_PACKAGE_INFO;
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uint32_t FUSE_OPT_VENDOR_CODE;
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uint32_t FUSE_OPT_FAB_CODE;
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uint32_t FUSE_OPT_LOT_CODE_0;
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uint32_t FUSE_OPT_LOT_CODE_1;
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uint32_t FUSE_OPT_WAFER_ID;
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uint32_t FUSE_OPT_X_COORDINATE;
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uint32_t FUSE_OPT_Y_COORDINATE;
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uint32_t FUSE_OPT_SEC_DEBUG_EN;
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uint32_t FUSE_OPT_OPS_RESERVED;
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uint32_t _0x224; /* Mariko only. */
|
|
uint32_t FUSE_GPU_IDDQ_CALIB;
|
|
uint32_t FUSE_TSENSOR3_CALIB;
|
|
uint32_t FUSE_CLOCK_BOUNDOUT0;
|
|
uint32_t FUSE_CLOCK_BOUNDOUT1;
|
|
uint32_t FUSE_RESERVED_ODM26[0x3]; /* Mariko only. */
|
|
uint32_t FUSE_OPT_SAMPLE_TYPE;
|
|
uint32_t FUSE_OPT_SUBREVISION;
|
|
uint32_t FUSE_OPT_SW_RESERVED_0;
|
|
uint32_t FUSE_OPT_SW_RESERVED_1;
|
|
uint32_t FUSE_TSENSOR4_CALIB;
|
|
uint32_t FUSE_TSENSOR5_CALIB;
|
|
uint32_t FUSE_TSENSOR6_CALIB;
|
|
uint32_t FUSE_TSENSOR7_CALIB;
|
|
uint32_t FUSE_OPT_PRIV_SEC_EN;
|
|
uint32_t FUSE_BOOT_SECURITY_INFO; /* Mariko only. */
|
|
uint32_t _0x26C; /* Mariko only. */
|
|
uint32_t _0x270; /* Mariko only. */
|
|
uint32_t _0x274; /* Mariko only. */
|
|
uint32_t _0x278; /* Mariko only. */
|
|
uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE;
|
|
uint32_t FUSE_TSENSOR_COMMON;
|
|
uint32_t FUSE_OPT_CP_BIN;
|
|
uint32_t FUSE_OPT_GPU_DISABLE;
|
|
uint32_t FUSE_OPT_FT_BIN;
|
|
uint32_t FUSE_OPT_DONE_MAP;
|
|
uint32_t FUSE_RESERVED_ODM29; /* Mariko only. */
|
|
uint32_t FUSE_APB2JTAG_DISABLE;
|
|
uint32_t FUSE_ODM_INFO;
|
|
uint32_t _0x2A0[0x2];
|
|
uint32_t FUSE_ARM_CRYPT_DE_FEATURE;
|
|
uint32_t _0x2AC;
|
|
uint32_t _0x2B0; /* Mariko only. */
|
|
uint32_t _0x2B4; /* Mariko only. */
|
|
uint32_t _0x2B8; /* Mariko only. */
|
|
uint32_t _0x2BC; /* Mariko only. */
|
|
uint32_t FUSE_WOA_SKU_FLAG;
|
|
uint32_t FUSE_ECO_RESERVE_1;
|
|
uint32_t FUSE_GCPLEX_CONFIG_FUSE;
|
|
uint32_t FUSE_PRODUCTION_MONTH;
|
|
uint32_t FUSE_RAM_REPAIR_INDICATOR;
|
|
uint32_t FUSE_TSENSOR9_CALIB;
|
|
uint32_t _0x2D8;
|
|
uint32_t FUSE_VMIN_CALIBRATION;
|
|
uint32_t FUSE_AGING_SENSOR_CALIBRATION;
|
|
uint32_t FUSE_DEBUG_AUTHENTICATION;
|
|
uint32_t FUSE_SECURE_PROVISION_INDEX;
|
|
uint32_t FUSE_SECURE_PROVISION_INFO;
|
|
uint32_t FUSE_OPT_GPU_DISABLE_CP1;
|
|
uint32_t FUSE_SPARE_ENDIS;
|
|
uint32_t FUSE_ECO_RESERVE_0;
|
|
uint32_t _0x2FC[0x2];
|
|
uint32_t FUSE_RESERVED_CALIB0;
|
|
uint32_t FUSE_RESERVED_CALIB1;
|
|
uint32_t FUSE_OPT_GPU_TPC0_DISABLE;
|
|
uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1;
|
|
uint32_t FUSE_OPT_CPU_DISABLE;
|
|
uint32_t FUSE_OPT_CPU_DISABLE_CP1;
|
|
uint32_t FUSE_TSENSOR10_CALIB;
|
|
uint32_t FUSE_TSENSOR10_CALIB_AUX;
|
|
uint32_t _0x324; /* Mariko only. */
|
|
uint32_t _0x328; /* Mariko only. */
|
|
uint32_t _0x32C; /* Mariko only. */
|
|
uint32_t _0x330; /* Mariko only. */
|
|
uint32_t _0x334; /* Mariko only. */
|
|
uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2;
|
|
uint32_t FUSE_OPT_GPU_TPC1_DISABLE;
|
|
uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1;
|
|
uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2;
|
|
uint32_t FUSE_OPT_CPU_DISABLE_CP2;
|
|
uint32_t FUSE_OPT_GPU_DISABLE_CP2;
|
|
uint32_t FUSE_USB_CALIB_EXT;
|
|
uint32_t FUSE_RESERVED_FIELD;
|
|
uint32_t _0x358[0x9];
|
|
uint32_t FUSE_SPARE_REALIGNMENT_REG;
|
|
uint32_t FUSE_SPARE_BIT[0x1E];
|
|
} tegra_fuse_chip_mariko_t;
|
|
|
|
static inline volatile tegra_fuse_t *fuse_get_regs(void)
|
|
{
|
|
return (volatile tegra_fuse_t *)FUSE_BASE;
|
|
}
|
|
|
|
static inline volatile tegra_fuse_chip_common_t *fuse_chip_common_get_regs(void)
|
|
{
|
|
return (volatile tegra_fuse_chip_common_t *)FUSE_CHIP_BASE;
|
|
}
|
|
|
|
static inline volatile tegra_fuse_chip_erista_t *fuse_chip_erista_get_regs(void)
|
|
{
|
|
return (volatile tegra_fuse_chip_erista_t *)FUSE_CHIP_BASE;
|
|
}
|
|
|
|
static inline volatile tegra_fuse_chip_mariko_t *fuse_chip_mariko_get_regs(void)
|
|
{
|
|
return (volatile tegra_fuse_chip_mariko_t *)FUSE_CHIP_BASE;
|
|
}
|
|
|
|
void fuse_init(void);
|
|
void fuse_disable_programming(void);
|
|
void fuse_disable_private_key(void);
|
|
void fuse_enable_power(void);
|
|
void fuse_disable_power(void);
|
|
|
|
uint32_t fuse_get_sku_info(void);
|
|
uint32_t fuse_get_spare_bit(uint32_t index);
|
|
uint32_t fuse_get_reserved_odm(uint32_t index);
|
|
uint32_t fuse_get_bootrom_patch_version(void);
|
|
uint64_t fuse_get_device_id(void);
|
|
uint32_t fuse_get_dram_id(void);
|
|
uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware);
|
|
uint32_t fuse_get_hardware_type(void);
|
|
uint32_t fuse_get_retail_type(void);
|
|
void fuse_get_hardware_info(void *dst);
|
|
bool fuse_is_new_format(void);
|
|
uint32_t fuse_get_device_unique_key_generation(void);
|
|
uint32_t fuse_get_soc_type(void);
|
|
uint32_t fuse_get_regulator(void);
|
|
|
|
uint32_t fuse_hw_read(uint32_t addr);
|
|
void fuse_hw_write(uint32_t value, uint32_t addr);
|
|
void fuse_hw_sense(void);
|
|
|
|
#endif
|