mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
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234 lines
7.4 KiB
C
234 lines
7.4 KiB
C
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef EXOSPHERE_FUSE_H
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#define EXOSPHERE_FUSE_H
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#include <stdbool.h>
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#include <stdint.h>
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#include "memory_map.h"
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/* Exosphere driver for the Tegra X1 FUSE registers. */
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typedef struct {
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uint32_t FUSE_FUSECTRL;
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uint32_t FUSE_FUSEADDR;
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uint32_t FUSE_FUSERDATA;
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uint32_t FUSE_FUSEWDATA;
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uint32_t FUSE_FUSETIME_RD1;
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uint32_t FUSE_FUSETIME_RD2;
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uint32_t FUSE_FUSETIME_PGM1;
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uint32_t FUSE_FUSETIME_PGM2;
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uint32_t FUSE_PRIV2INTFC_START;
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uint32_t FUSE_FUSEBYPASS;
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uint32_t FUSE_PRIVATEKEYDISABLE;
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uint32_t FUSE_DISABLEREGPROGRAM;
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uint32_t FUSE_WRITE_ACCESS_SW;
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uint32_t FUSE_PWR_GOOD_SW;
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uint32_t _0x38;
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uint32_t FUSE_PRIV2RESHIFT;
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uint32_t _0x40[0x3];
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uint32_t FUSE_FUSETIME_RD3;
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uint32_t _0x50[0xC];
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uint32_t FUSE_PRIVATE_KEY0_NONZERO;
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uint32_t FUSE_PRIVATE_KEY1_NONZERO;
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uint32_t FUSE_PRIVATE_KEY2_NONZERO;
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uint32_t FUSE_PRIVATE_KEY3_NONZERO;
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uint32_t FUSE_PRIVATE_KEY4_NONZERO;
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uint32_t _0x90[0x1C];
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} tegra_fuse_t;
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typedef struct {
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uint32_t FUSE_PRODUCTION_MODE;
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uint32_t FUSE_JTAG_SECUREID_VALID;
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uint32_t FUSE_ODM_LOCK;
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uint32_t FUSE_OPT_OPENGL_EN;
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uint32_t FUSE_SKU_INFO;
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uint32_t FUSE_CPU_SPEEDO_0_CALIB;
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uint32_t FUSE_CPU_IDDQ_CALIB;
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uint32_t FUSE_DAC_CRT_CALIB;
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uint32_t FUSE_DAC_HDTV_CALIB;
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uint32_t FUSE_DAC_SDTV_CALIB;
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uint32_t FUSE_OPT_FT_REV;
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uint32_t FUSE_CPU_SPEEDO_1_CALIB;
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uint32_t FUSE_CPU_SPEEDO_2_CALIB;
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uint32_t FUSE_SOC_SPEEDO_0_CALIB;
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uint32_t FUSE_SOC_SPEEDO_1_CALIB;
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uint32_t FUSE_SOC_SPEEDO_2_CALIB;
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uint32_t FUSE_SOC_IDDQ_CALIB;
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uint32_t FUSE_RESERVED_PRODUCTION_WP;
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uint32_t FUSE_FA;
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uint32_t FUSE_RESERVED_PRODUCTION;
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uint32_t FUSE_HDMI_LANE0_CALIB;
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uint32_t FUSE_HDMI_LANE1_CALIB;
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uint32_t FUSE_HDMI_LANE2_CALIB;
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uint32_t FUSE_HDMI_LANE3_CALIB;
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uint32_t FUSE_ENCRYPTION_RATE;
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uint32_t FUSE_PUBLIC_KEY[0x8];
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uint32_t FUSE_TSENSOR1_CALIB;
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uint32_t FUSE_TSENSOR2_CALIB;
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uint32_t FUSE_VSENSOR_CALIB;
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uint32_t FUSE_OPT_CP_REV;
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uint32_t FUSE_OPT_PFG;
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uint32_t FUSE_TSENSOR0_CALIB;
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uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE;
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uint32_t FUSE_SECURITY_MODE;
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uint32_t FUSE_PRIVATE_KEY[0x5];
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uint32_t FUSE_ARM_JTAG_DIS;
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uint32_t FUSE_BOOT_DEVICE_INFO;
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uint32_t FUSE_RESERVED_SW;
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uint32_t FUSE_OPT_VP9_DISABLE;
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uint32_t FUSE_RESERVED_ODM[0x8];
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uint32_t FUSE_OBS_DIS;
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uint32_t FUSE_NOR_INFO;
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uint32_t FUSE_USB_CALIB;
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uint32_t FUSE_SKU_DIRECT_CONFIG;
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uint32_t FUSE_KFUSE_PRIVKEY_CTRL;
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uint32_t FUSE_PACKAGE_INFO;
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uint32_t FUSE_OPT_VENDOR_CODE;
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uint32_t FUSE_OPT_FAB_CODE;
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uint32_t FUSE_OPT_LOT_CODE_0;
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uint32_t FUSE_OPT_LOT_CODE_1;
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uint32_t FUSE_OPT_WAFER_ID;
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uint32_t FUSE_OPT_X_COORDINATE;
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uint32_t FUSE_OPT_Y_COORDINATE;
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uint32_t FUSE_OPT_SEC_DEBUG_EN;
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uint32_t FUSE_OPT_OPS_RESERVED;
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uint32_t FUSE_SATA_CALIB;
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uint32_t FUSE_GPU_IDDQ_CALIB;
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uint32_t FUSE_TSENSOR3_CALIB;
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uint32_t FUSE_SKU_BOND_OUT_L;
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uint32_t FUSE_SKU_BOND_OUT_H;
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uint32_t FUSE_SKU_BOND_OUT_U;
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uint32_t FUSE_SKU_BOND_OUT_V;
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uint32_t FUSE_SKU_BOND_OUT_W;
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uint32_t FUSE_OPT_SAMPLE_TYPE;
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uint32_t FUSE_OPT_SUBREVISION;
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uint32_t FUSE_OPT_SW_RESERVED_0;
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uint32_t FUSE_OPT_SW_RESERVED_1;
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uint32_t FUSE_TSENSOR4_CALIB;
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uint32_t FUSE_TSENSOR5_CALIB;
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uint32_t FUSE_TSENSOR6_CALIB;
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uint32_t FUSE_TSENSOR7_CALIB;
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uint32_t FUSE_OPT_PRIV_SEC_EN;
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uint32_t FUSE_PKC_DISABLE;
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uint32_t _0x16C;
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uint32_t _0x170;
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uint32_t _0x174;
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uint32_t _0x178;
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uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE;
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uint32_t FUSE_TSENSOR_COMMON;
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uint32_t FUSE_OPT_CP_BIN;
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uint32_t FUSE_OPT_GPU_DISABLE;
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uint32_t FUSE_OPT_FT_BIN;
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uint32_t FUSE_OPT_DONE_MAP;
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uint32_t _0x194;
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uint32_t FUSE_APB2JTAG_DISABLE;
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uint32_t FUSE_ODM_INFO;
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uint32_t _0x1A0;
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uint32_t _0x1A4;
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uint32_t FUSE_ARM_CRYPT_DE_FEATURE;
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uint32_t _0x1AC;
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uint32_t _0x1B0;
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uint32_t _0x1B4;
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uint32_t _0x1B8;
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uint32_t _0x1BC;
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uint32_t FUSE_WOA_SKU_FLAG;
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uint32_t FUSE_ECO_RESERVE_1;
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uint32_t FUSE_GCPLEX_CONFIG_FUSE;
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uint32_t FUSE_PRODUCTION_MONTH;
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uint32_t FUSE_RAM_REPAIR_INDICATOR;
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uint32_t FUSE_TSENSOR9_CALIB;
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uint32_t _0x1D8;
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uint32_t FUSE_VMIN_CALIBRATION;
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uint32_t FUSE_AGING_SENSOR_CALIBRATION;
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uint32_t FUSE_DEBUG_AUTHENTICATION;
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uint32_t FUSE_SECURE_PROVISION_INDEX;
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uint32_t FUSE_SECURE_PROVISION_INFO;
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uint32_t FUSE_OPT_GPU_DISABLE_CP1;
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uint32_t FUSE_SPARE_ENDIS;
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uint32_t FUSE_ECO_RESERVE_0;
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uint32_t _0x1FC;
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uint32_t _0x200;
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uint32_t FUSE_RESERVED_CALIB0;
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uint32_t FUSE_RESERVED_CALIB1;
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uint32_t FUSE_OPT_GPU_TPC0_DISABLE;
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uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1;
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uint32_t FUSE_OPT_CPU_DISABLE;
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uint32_t FUSE_OPT_CPU_DISABLE_CP1;
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uint32_t FUSE_TSENSOR10_CALIB;
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uint32_t FUSE_TSENSOR10_CALIB_AUX;
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uint32_t FUSE_OPT_RAM_SVOP_DP;
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uint32_t FUSE_OPT_RAM_SVOP_PDP;
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uint32_t FUSE_OPT_RAM_SVOP_REG;
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uint32_t FUSE_OPT_RAM_SVOP_SP;
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uint32_t FUSE_OPT_RAM_SVOP_SMPDP;
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uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2;
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uint32_t FUSE_OPT_GPU_TPC1_DISABLE;
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uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1;
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uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2;
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uint32_t FUSE_OPT_CPU_DISABLE_CP2;
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uint32_t FUSE_OPT_GPU_DISABLE_CP2;
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uint32_t FUSE_USB_CALIB_EXT;
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uint32_t FUSE_RESERVED_FIELD;
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uint32_t FUSE_OPT_ECC_EN;
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uint32_t _0x25C;
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uint32_t _0x260;
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uint32_t _0x264;
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uint32_t _0x268;
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uint32_t _0x26C;
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uint32_t _0x270;
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uint32_t _0x274;
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uint32_t _0x278;
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uint32_t FUSE_SPARE_REALIGNMENT_REG;
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uint32_t FUSE_SPARE_BIT[0x20];
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} tegra_fuse_chip_t;
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static inline volatile tegra_fuse_t *fuse_get_regs(void) {
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return (volatile tegra_fuse_t *)(MMIO_GET_DEVICE_ADDRESS(MMIO_DEVID_FUSE) + 0x800);
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}
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static inline volatile tegra_fuse_chip_t *fuse_chip_get_regs(void) {
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return (volatile tegra_fuse_chip_t *)(MMIO_GET_DEVICE_ADDRESS(MMIO_DEVID_FUSE) + 0x900);
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}
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#define FUSE_REGS (fuse_get_regs())
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#define FUSE_CHIP_REGS (fuse_chip_get_regs())
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void fuse_init(void);
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void fuse_disable_programming(void);
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void fuse_disable_private_key(void);
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uint32_t fuse_get_sku_info(void);
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uint32_t fuse_get_spare_bit(uint32_t idx);
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uint32_t fuse_get_reserved_odm(uint32_t idx);
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uint32_t fuse_get_bootrom_patch_version(void);
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uint64_t fuse_get_device_id(void);
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uint32_t fuse_get_dram_id(void);
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uint32_t fuse_get_hardware_type(uint32_t target_firmware);
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uint32_t fuse_get_retail_type(void);
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void fuse_get_hardware_info(void *dst);
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uint32_t fuse_get_5x_key_generation(void);
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bool fuse_has_rcm_bug_patch(void);
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uint32_t fuse_hw_read(uint32_t addr);
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void fuse_hw_write(uint32_t value, uint32_t addr);
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void fuse_hw_sense(void);
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uint32_t fuse_get_expected_fuse_version(uint32_t target_firmware);
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#endif
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