mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-11-23 12:22:08 +00:00
188 lines
5.3 KiB
C
188 lines
5.3 KiB
C
/*
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* Copyright (c) 2018 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef EXOSPHERE_WARMBOOT_BIN_SE_H
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#define EXOSPHERE_WARMBOOT_BIN_SE_H
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#define SE_BASE 0x70012000
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#define MAKE_SE_REG(n) MAKE_REG32(SE_BASE + n)
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#define KEYSLOT_SWITCH_LP0TZRAMKEY 0x2
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#define KEYSLOT_SWITCH_SRKGENKEY 0x8
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#define KEYSLOT_SWITCH_PACKAGE2KEY 0x8
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#define KEYSLOT_SWITCH_TEMPKEY 0x9
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#define KEYSLOT_SWITCH_SESSIONKEY 0xA
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#define KEYSLOT_SWITCH_RNGKEY 0xB
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#define KEYSLOT_SWITCH_MASTERKEY 0xC
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#define KEYSLOT_SWITCH_DEVICEKEY 0xD
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/* This keyslot was added in 4.0.0. */
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#define KEYSLOT_SWITCH_4XNEWDEVICEKEYGENKEY 0xD
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#define KEYSLOT_SWITCH_4XNEWCONSOLEKEYGENKEY 0xE
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#define KEYSLOT_SWITCH_4XOLDDEVICEKEY 0xF
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/* This keyslot was added in 5.0.0. */
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#define KEYSLOT_SWITCH_5XNEWDEVICEKEYGENKEY 0xA
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#define KEYSLOT_AES_MAX 0x10
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#define KEYSLOT_RSA_MAX 0x2
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#define KEYSIZE_AES_MAX 0x20
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#define KEYSIZE_RSA_MAX 0x100
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#define ALG_SHIFT (12)
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#define ALG_DEC_SHIFT (8)
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#define ALG_NOP (0 << ALG_SHIFT)
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#define ALG_AES_ENC (1 << ALG_SHIFT)
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#define ALG_AES_DEC ((1 << ALG_DEC_SHIFT) | ALG_NOP)
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#define ALG_RNG (2 << ALG_SHIFT)
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#define ALG_SHA (3 << ALG_SHIFT)
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#define ALG_RSA (4 << ALG_SHIFT)
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#define DST_SHIFT (2)
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#define DST_MEMORY (0 << DST_SHIFT)
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#define DST_HASHREG (1 << DST_SHIFT)
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#define DST_KEYTAB (2 << DST_SHIFT)
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#define DST_SRK (3 << DST_SHIFT)
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#define DST_RSAREG (4 << DST_SHIFT)
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#define ENCMODE_SHIFT (24)
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#define DECMODE_SHIFT (16)
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#define ENCMODE_SHA256 (5 << ENCMODE_SHIFT)
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#define HASH_DISABLE (0x0)
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#define HASH_ENABLE (0x1)
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#define OP_ABORT 0
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#define OP_START 1
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#define OP_RESTART 2
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#define OP_CTX_SAVE 3
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#define OP_RESTART_IN 4
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#define CTX_SAVE_SRC_SHIFT 29
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#define CTX_SAVE_SRC_STICKY_BITS (0 << CTX_SAVE_SRC_SHIFT)
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#define CTX_SAVE_SRC_KEYTABLE_AES (2 << CTX_SAVE_SRC_SHIFT)
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#define CTX_SAVE_SRC_KEYTABLE_RSA (1 << CTX_SAVE_SRC_SHIFT)
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#define CTX_SAVE_SRC_MEM (4 << CTX_SAVE_SRC_SHIFT)
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#define CTX_SAVE_SRC_SRK (6 << CTX_SAVE_SRC_SHIFT)
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#define CTX_SAVE_KEY_LOW_BITS 0
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#define CTX_SAVE_KEY_HIGH_BITS 1
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#define CTX_SAVE_KEY_ORIGINAL_IV 2
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#define CTX_SAVE_KEY_UPDATED_IV 3
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#define CTX_SAVE_STICKY_BIT_INDEX_SHIFT 24
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#define CTX_SAVE_KEY_INDEX_SHIFT 8
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#define CTX_SAVE_RSA_KEY_INDEX_SHIFT 16
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#define CTX_SAVE_RSA_KEY_BLOCK_INDEX_SHIFT 12
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#define RSA_2048_BYTES 0x100
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typedef struct {
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uint32_t _0x0;
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uint32_t _0x4;
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uint32_t OPERATION_REG;
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uint32_t INT_ENABLE_REG;
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uint32_t INT_STATUS_REG;
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uint32_t CONFIG_REG;
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uint32_t IN_LL_ADDR_REG;
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uint32_t _0x1C;
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uint32_t _0x20;
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uint32_t OUT_LL_ADDR_REG;
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uint32_t _0x28;
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uint32_t _0x2C;
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uint8_t HASH_RESULT_REG[0x20];
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uint8_t _0x50[0x20];
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uint32_t CONTEXT_SAVE_CONFIG_REG;
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uint8_t _0x74[0x18C];
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uint32_t SHA_CONFIG_REG;
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uint32_t SHA_MSG_LENGTH_REG;
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uint32_t _0x208;
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uint32_t _0x20C;
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uint32_t _0x210;
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uint32_t SHA_MSG_LEFT_REG;
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uint32_t _0x218;
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uint32_t _0x21C;
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uint32_t _0x220;
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uint32_t _0x224;
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uint8_t _0x228[0x58];
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uint32_t AES_KEY_READ_DISABLE_REG;
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uint32_t AES_KEYSLOT_FLAGS[0x10];
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uint8_t _0x2C4[0x3C];
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uint32_t _0x300;
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uint32_t CRYPTO_REG;
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uint32_t CRYPTO_CTR_REG[4];
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uint32_t BLOCK_COUNT_REG;
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uint32_t AES_KEYTABLE_ADDR;
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uint32_t AES_KEYTABLE_DATA;
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uint32_t _0x324;
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uint32_t _0x328;
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uint32_t _0x32C;
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uint32_t CRYPTO_KEYTABLE_DST_REG;
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uint8_t _0x334[0xC];
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uint32_t RNG_CONFIG_REG;
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uint32_t RNG_SRC_CONFIG_REG;
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uint32_t RNG_RESEED_INTERVAL_REG;
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uint8_t _0x34C[0xB4];
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uint32_t RSA_CONFIG;
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uint32_t RSA_KEY_SIZE_REG;
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uint32_t RSA_EXP_SIZE_REG;
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uint32_t RSA_KEY_READ_DISABLE_REG;
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uint32_t RSA_KEYSLOT_FLAGS[2];
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uint32_t _0x418;
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uint32_t _0x41C;
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uint32_t RSA_KEYTABLE_ADDR;
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uint32_t RSA_KEYTABLE_DATA;
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uint8_t RSA_OUTPUT[0x100];
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uint8_t _0x528[0x2D8];
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uint32_t FLAGS_REG;
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uint32_t ERR_STATUS_REG;
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uint32_t _0x808;
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uint32_t SPARE_0;
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uint32_t _0x810;
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uint32_t _0x814;
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uint32_t _0x818;
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uint32_t _0x81C;
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uint8_t _0x820[0x17E0];
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} tegra_se_t;
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typedef struct {
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uint32_t address;
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uint32_t size;
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} se_addr_info_t;
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typedef struct {
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uint32_t num_entries; /* Set to total entries - 1 */
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se_addr_info_t addr_info; /* This should really be an array...but for our use case it works. */
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} se_ll_t;
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static inline volatile tegra_se_t *se_get_regs(void) {
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return (volatile tegra_se_t *)SE_BASE;
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}
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void se_check_error_status_reg(void);
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void se_check_for_error(void);
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void se_verify_flags_cleared(void);
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void clear_aes_keyslot(unsigned int keyslot);
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void clear_rsa_keyslot(unsigned int keyslot);
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void clear_aes_keyslot_iv(unsigned int keyslot);
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void se_compute_aes_256_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, const void *data, size_t data_size);
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void se_aes_256_cbc_decrypt(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size);
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#endif
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