mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-11-18 18:06:40 +00:00
163 lines
7.4 KiB
C
163 lines
7.4 KiB
C
#include <string.h>
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#include "utils.h"
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#include "mmu.h"
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#include "memory_map.h"
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#include "arm.h"
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extern const uint8_t __start_cold[];
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extern const uint8_t __warmboot_crt0_start__[], __warmboot_crt0_end__[], __warmboot_crt0_lma__[];
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extern const uint8_t __main_start__[], __main_bss_start__[], __main_end__[], __main_lma__[];
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extern const uint8_t __pk2ldr_start__[], __pk2ldr_bss_start__[], __pk2ldr_end__[], __pk2ldr_lma__[];
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extern const uint8_t __vectors_start__[], __vectors_end__[], __vectors_lma__[];
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/* warmboot_init.c */
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void set_memory_registers_enable_mmu(void);
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static void identity_map_all_mappings(uintptr_t *mmu_l1_tbl, uintptr_t *mmu_l3_tbl) {
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static const uintptr_t addrs[] = { TUPLE_FOLD_LEFT_0(EVAL(IDENTIY_MAPPING_ID_MAX), _MMAPID, COMMA) };
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static const size_t sizes[] = { TUPLE_FOLD_LEFT_1(EVAL(IDENTIY_MAPPING_ID_MAX), _MMAPID, COMMA) };
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static const uint64_t attribs[] = { TUPLE_FOLD_LEFT_2(EVAL(IDENTIY_MAPPING_ID_MAX), _MMAPID, COMMA) };
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static const uint64_t is_block[] = { TUPLE_FOLD_LEFT_3(EVAL(IDENTIY_MAPPING_ID_MAX), _MMAPID, COMMA) };
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for(size_t i = 0; i < IDENTIY_MAPPING_ID_MAX; i++) {
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identity_map_mapping(mmu_l1_tbl, mmu_l3_tbl, addrs[i], sizes[i], attribs[i], is_block[i]);
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}
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}
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static void mmio_map_all_devices(uintptr_t *mmu_l3_tbl) {
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static const uintptr_t pas[] = { TUPLE_FOLD_LEFT_0(EVAL(MMIO_DEVID_MAX), _MMAPDEV, COMMA) };
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static const size_t sizes[] = { TUPLE_FOLD_LEFT_1(EVAL(MMIO_DEVID_MAX), _MMAPDEV, COMMA) };
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static const bool is_secure[] = { TUPLE_FOLD_LEFT_2(EVAL(MMIO_DEVID_MAX), _MMAPDEV, COMMA) };
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for(size_t i = 0, offset = 0; i < MMIO_DEVID_MAX; i++) {
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mmio_map_device(mmu_l3_tbl, MMIO_BASE + offset, pas[i], sizes[i], is_secure[i]);
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offset += sizes[i];
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offset += 0x1000;
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}
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}
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static void lp0_entry_map_all_ram_segments(uintptr_t *mmu_l3_tbl) {
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static const uintptr_t pas[] = { TUPLE_FOLD_LEFT_0(EVAL(LP0_ENTRY_RAM_SEGMENT_ID_MAX), _MMAPLP0ES, COMMA) };
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static const size_t sizes[] = { TUPLE_FOLD_LEFT_1(EVAL(LP0_ENTRY_RAM_SEGMENT_ID_MAX), _MMAPLP0ES, COMMA) };
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static const uint64_t attribs[] = { TUPLE_FOLD_LEFT_2(EVAL(LP0_ENTRY_RAM_SEGMENT_ID_MAX), _MMAPLP0ES, COMMA) };
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for(size_t i = 0, offset = 0; i < LP0_ENTRY_RAM_SEGMENT_ID_MAX; i++) {
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lp0_entry_map_ram_segment(mmu_l3_tbl, LP0_ENTRY_RAM_SEGMENT_BASE + offset, pas[i], sizes[i], attribs[i]);
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offset += 0x10000;
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}
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}
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static void warmboot_map_all_ram_segments(uintptr_t *mmu_l3_tbl) {
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static const uintptr_t pas[] = { TUPLE_FOLD_LEFT_0(EVAL(WARMBOOT_RAM_SEGMENT_ID_MAX), _MMAPWBS, COMMA) };
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static const size_t sizes[] = { TUPLE_FOLD_LEFT_1(EVAL(WARMBOOT_RAM_SEGMENT_ID_MAX), _MMAPWBS, COMMA) };
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static const uint64_t attribs[] = { TUPLE_FOLD_LEFT_2(EVAL(WARMBOOT_RAM_SEGMENT_ID_MAX), _MMAPWBS, COMMA) };
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for(size_t i = 0, offset = 0; i < WARMBOOT_RAM_SEGMENT_ID_MAX; i++) {
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warmboot_map_ram_segment(mmu_l3_tbl, WARMBOOT_RAM_SEGMENT_BASE + offset, pas[i], sizes[i], attribs[i]);
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offset += sizes[i];
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}
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}
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static void tzram_map_all_segments(uintptr_t *mmu_l3_tbl) {
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static const uintptr_t offs[] = { TUPLE_FOLD_LEFT_0(EVAL(TZRAM_SEGMENT_ID_MAX), _MMAPTZS, COMMA) };
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static const size_t sizes[] = { TUPLE_FOLD_LEFT_1(EVAL(TZRAM_SEGMENT_ID_MAX), _MMAPTZS, COMMA) };
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static const size_t increments[] = { TUPLE_FOLD_LEFT_2(EVAL(TZRAM_SEGMENT_ID_MAX), _MMAPTZS, COMMA) };
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static const bool is_executable[] = { TUPLE_FOLD_LEFT_3(EVAL(TZRAM_SEGMENT_ID_MAX), _MMAPTZS, COMMA) };
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for(size_t i = 0, offset = 0; i < TZRAM_SEGMENT_ID_MAX; i++) {
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tzram_map_segment(mmu_l3_tbl, TZRAM_SEGMENT_BASE, 0x7C010000ull + offs[i], sizes[i], is_executable[i]);
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offset += increments[i];
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}
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}
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static void configure_ttbls(void) {
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uintptr_t *mmu_l1_tbl = (uintptr_t *)(TZRAM_GET_SEGMENT_PA(TZRAM_SEGEMENT_ID_SECMON_EVT) + 0x800 - 64);
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uintptr_t *mmu_l2_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_L2_TRANSLATION_TABLE);
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uintptr_t *mmu_l3_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_L3_TRANSLATION_TABLE);
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mmu_init_table(mmu_l1_tbl, 64); /* 33-bit address space */
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mmu_init_table(mmu_l2_tbl, 4096);
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/*
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Nintendo uses the same L3 table for everything, but they make sure
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nothing clashes.
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*/
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mmu_init_table(mmu_l3_tbl, 4096);
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mmu_map_table(1, mmu_l1_tbl, 0x40000000, mmu_l2_tbl, 0);
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mmu_map_table(1, mmu_l1_tbl, 0x1C0000000, mmu_l2_tbl, 0);
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mmu_map_table(2, mmu_l2_tbl, 0x40000000, mmu_l3_tbl, 0);
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mmu_map_table(2, mmu_l2_tbl, 0x7C000000, mmu_l3_tbl, 0);
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mmu_map_table(2, mmu_l2_tbl, 0x1F0000000ull, mmu_l3_tbl, 0);
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identity_map_all_mappings(mmu_l1_tbl, mmu_l3_tbl);
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mmio_map_all_devices(mmu_l3_tbl);
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lp0_entry_map_all_ram_segments(mmu_l3_tbl);
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warmboot_map_all_ram_segments(mmu_l3_tbl);
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tzram_map_all_segments(mmu_l3_tbl);
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}
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__attribute__((noinline)) static void copy_lma_to_vma(const void *vma, const void *lma, size_t size) {
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uint64_t *p_vma = (uint64_t *)vma;
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const uint64_t *p_lma = (const uint64_t *)((size_t)lma + __start_cold);
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for (size_t i = 0; i < size / 8; i++) {
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p_vma[i] = p_lma[i];
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}
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}
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FAR_REACHING static void copy_warmboot_crt0(void) {
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copy_lma_to_vma(__warmboot_crt0_start__, __warmboot_crt0_lma__, __warmboot_crt0_end__ - __warmboot_crt0_start__);
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}
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FAR_REACHING static void copy_other_sections(void) {
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copy_lma_to_vma(__main_start__, __main_lma__, __main_end__ - __main_start__);
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copy_lma_to_vma(__pk2ldr_start__, __pk2ldr_lma__, __pk2ldr_end__ - __pk2ldr_start__);
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copy_lma_to_vma(__vectors_start__, __vectors_lma__, __vectors_end__ - __vectors_start__);
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}
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FAR_REACHING static void set_memory_registers_enable_mmu_tzram_pa(void) {
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volatile uintptr_t v = (uintptr_t)set_memory_registers_enable_mmu;
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((void (*)(void))v)();
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}
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FAR_REACHING static void flush_dcache_all_tzram_pa(void) {
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uintptr_t pa = TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_WARMBOOT_CRT0_AND_MAIN);
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uintptr_t main_pa = pa | ((uintptr_t)__main_start__ & 0xFFF);
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uintptr_t v = (uintptr_t)flush_dcache_all - (uintptr_t)__main_start__ + (uintptr_t)main_pa;
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((void (*)(void))v)();
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}
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FAR_REACHING static void invalidate_icache_all_inner_shareable_tzram_pa(void) {
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uintptr_t pa = TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_WARMBOOT_CRT0_AND_MAIN);
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uintptr_t main_pa = pa | ((uintptr_t)__main_start__ & 0xFFF);
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uintptr_t v = (uintptr_t)invalidate_icache_all_inner_shareable - (uintptr_t)__main_start__ + (uintptr_t)main_pa;
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((void (*)(void))v)();
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}
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FAR_REACHING static void clear_bss(void) {
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memset((void *)__pk2ldr_bss_start__, 0, __pk2ldr_end__ - __pk2ldr_bss_start__);
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memset((void *)__main_bss_start__, 0, __main_end__ - __main_bss_start__);
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}
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uintptr_t get_coldboot_crt0_stack_address(void) {
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return TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_CORE3_STACK) + 0x800;
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}
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void coldboot_init(void) {
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/* TODO: Set NX BOOTLOADER clock time field */
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copy_warmboot_crt0();
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/* At this point, we can (and will) access functions located in .warm_crt0 */
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/* TODO: initialize DMA controllers, etc. */
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configure_ttbls();
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copy_other_sections();
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set_memory_registers_enable_mmu_tzram_pa();
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flush_dcache_all_tzram_pa();
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invalidate_icache_all_inner_shareable_tzram_pa();
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/* At this point we can access all the mapped segments (all other functions, data...) normally */
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clear_bss();
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}
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