mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-11-23 12:22:08 +00:00
260 lines
8.2 KiB
C++
260 lines
8.2 KiB
C++
/*
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* Copyright (c) Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include <vapours.hpp>
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#include <mesosphere/arch/arm64/kern_cpu_system_registers.hpp>
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#include <mesosphere/kern_select_userspace_memory_access.hpp>
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namespace ams::kern::arch::arm64::cpu {
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#if defined(ATMOSPHERE_CPU_ARM_CORTEX_A57) || defined(ATMOSPHERE_CPU_ARM_CORTEX_A53)
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constexpr inline size_t InstructionCacheLineSize = 0x40;
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constexpr inline size_t DataCacheLineSize = 0x40;
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constexpr inline size_t NumPerformanceCounters = 6;
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#else
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#error "Unknown CPU for cache line sizes"
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#endif
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#if defined(ATMOSPHERE_BOARD_NINTENDO_NX)
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constexpr inline size_t NumCores = 4;
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#elif defined(ATMOSPHERE_BOARD_QEMU_VIRT)
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constexpr inline size_t NumCores = 4;
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#else
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#error "Unknown Board for cpu::NumCores"
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#endif
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/* Initialization. */
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NOINLINE void InitializeInterruptThreads(s32 core_id);
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/* Helpers for managing memory state. */
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ALWAYS_INLINE void DataSynchronizationBarrier() {
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__asm__ __volatile__("dsb sy" ::: "memory");
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}
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ALWAYS_INLINE void DataSynchronizationBarrierInnerShareable() {
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__asm__ __volatile__("dsb ish" ::: "memory");
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}
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ALWAYS_INLINE void DataSynchronizationBarrierInnerShareableStore() {
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__asm__ __volatile__("dsb ishst" ::: "memory");
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}
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ALWAYS_INLINE void DataMemoryBarrier() {
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__asm__ __volatile__("dmb sy" ::: "memory");
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}
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ALWAYS_INLINE void DataMemoryBarrierInnerShareable() {
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__asm__ __volatile__("dmb ish" ::: "memory");
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}
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ALWAYS_INLINE void DataMemoryBarrierInnerShareableStore() {
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__asm__ __volatile__("dmb ishst" ::: "memory");
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}
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ALWAYS_INLINE void InstructionMemoryBarrier() {
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__asm__ __volatile__("isb" ::: "memory");
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}
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ALWAYS_INLINE void EnsureInstructionConsistency() {
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DataSynchronizationBarrierInnerShareable();
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InstructionMemoryBarrier();
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}
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ALWAYS_INLINE void EnsureInstructionConsistencyFullSystem() {
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DataSynchronizationBarrier();
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InstructionMemoryBarrier();
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}
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ALWAYS_INLINE void Yield() {
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__asm__ __volatile__("yield" ::: "memory");
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}
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ALWAYS_INLINE void SwitchProcess(u64 ttbr, u32 proc_id) {
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SetTtbr0El1(ttbr);
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ContextIdRegisterAccessor(0).SetProcId(proc_id).Store();
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InstructionMemoryBarrier();
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}
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/* Performance counter helpers. */
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ALWAYS_INLINE u64 GetCycleCounter() {
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return cpu::GetPmcCntrEl0();
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}
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ALWAYS_INLINE u32 GetPerformanceCounter(s32 n) {
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u64 counter = 0;
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if (n < static_cast<s32>(NumPerformanceCounters)) {
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switch (n) {
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case 0:
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counter = cpu::GetPmevCntr0El0();
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break;
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case 1:
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counter = cpu::GetPmevCntr1El0();
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break;
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case 2:
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counter = cpu::GetPmevCntr2El0();
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break;
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case 3:
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counter = cpu::GetPmevCntr3El0();
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break;
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case 4:
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counter = cpu::GetPmevCntr4El0();
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break;
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case 5:
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counter = cpu::GetPmevCntr5El0();
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break;
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default:
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break;
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}
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}
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return static_cast<u32>(counter);
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}
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/* Helper for address access. */
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ALWAYS_INLINE bool GetPhysicalAddressWritable(KPhysicalAddress *out, KVirtualAddress addr, bool privileged = false) {
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const uintptr_t va = GetInteger(addr);
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if (privileged) {
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__asm__ __volatile__("at s1e1w, %[va]" :: [va]"r"(va) : "memory");
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} else {
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__asm__ __volatile__("at s1e0w, %[va]" :: [va]"r"(va) : "memory");
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}
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InstructionMemoryBarrier();
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u64 par = GetParEl1();
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if (par & 0x1) {
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return false;
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}
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if (out) {
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*out = KPhysicalAddress((par & 0xFFFFFFFFF000ull) | (va & 0xFFFull));
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}
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return true;
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}
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ALWAYS_INLINE bool GetPhysicalAddressReadable(KPhysicalAddress *out, KVirtualAddress addr, bool privileged = false) {
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const uintptr_t va = GetInteger(addr);
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if (privileged) {
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__asm__ __volatile__("at s1e1r, %[va]" :: [va]"r"(va) : "memory");
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} else {
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__asm__ __volatile__("at s1e0r, %[va]" :: [va]"r"(va) : "memory");
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}
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InstructionMemoryBarrier();
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u64 par = GetParEl1();
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if (par & 0x1) {
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return false;
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}
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if (out) {
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*out = KPhysicalAddress((par & 0xFFFFFFFFF000ull) | (va & 0xFFFull));
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}
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return true;
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}
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ALWAYS_INLINE bool CanAccessAtomic(KProcessAddress addr, bool privileged = false) {
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const uintptr_t va = GetInteger(addr);
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if (privileged) {
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__asm__ __volatile__("at s1e1w, %[va]" :: [va]"r"(va) : "memory");
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} else {
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__asm__ __volatile__("at s1e0w, %[va]" :: [va]"r"(va) : "memory");
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}
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InstructionMemoryBarrier();
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u64 par = GetParEl1();
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if (par & 0x1) {
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return false;
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}
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return (par >> (BITSIZEOF(par) - BITSIZEOF(u8))) == 0xFF;
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}
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/* Synchronization helpers. */
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NOINLINE void SynchronizeAllCores();
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void SynchronizeCores(u64 core_mask);
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/* Cache management helpers. */
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void StoreCacheForInit(void *addr, size_t size);
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void FlushEntireDataCache();
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Result InvalidateDataCache(void *addr, size_t size);
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Result StoreDataCache(const void *addr, size_t size);
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Result FlushDataCache(const void *addr, size_t size);
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void InvalidateEntireInstructionCache();
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void ClearPageToZeroImpl(void *);
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ALWAYS_INLINE void ClearPageToZero(void * const page) {
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MESOSPHERE_ASSERT(util::IsAligned(reinterpret_cast<uintptr_t>(page), PageSize));
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MESOSPHERE_ASSERT(page != nullptr);
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ClearPageToZeroImpl(page);
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}
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ALWAYS_INLINE void InvalidateTlbByAsid(u32 asid) {
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const u64 value = (static_cast<u64>(asid) << 48);
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__asm__ __volatile__("tlbi aside1is, %[value]" :: [value]"r"(value) : "memory");
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EnsureInstructionConsistency();
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}
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ALWAYS_INLINE void InvalidateTlbByAsidAndVa(u32 asid, KProcessAddress virt_addr) {
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const u64 value = (static_cast<u64>(asid) << 48) | ((GetInteger(virt_addr) >> 12) & 0xFFFFFFFFFFFul);
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__asm__ __volatile__("tlbi aside1is, %[value]" :: [value]"r"(value) : "memory");
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EnsureInstructionConsistency();
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}
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ALWAYS_INLINE void InvalidateEntireTlb() {
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__asm__ __volatile__("tlbi vmalle1is" ::: "memory");
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EnsureInstructionConsistency();
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}
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ALWAYS_INLINE void InvalidateEntireTlbDataOnly() {
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__asm__ __volatile__("tlbi vmalle1is" ::: "memory");
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DataSynchronizationBarrierInnerShareable();
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}
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ALWAYS_INLINE void InvalidateTlbByVaDataOnly(KProcessAddress virt_addr) {
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const u64 value = ((GetInteger(virt_addr) >> 12) & 0xFFFFFFFFFFFul);
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__asm__ __volatile__("tlbi vaae1is, %[value]" :: [value]"r"(value) : "memory");
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DataSynchronizationBarrierInnerShareable();
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}
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ALWAYS_INLINE uintptr_t GetCurrentThreadPointerValue() {
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register uintptr_t x18 asm("x18");
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__asm__ __volatile__("" : [x18]"=r"(x18));
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return x18;
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}
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ALWAYS_INLINE void SetCurrentThreadPointerValue(uintptr_t value) {
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register uintptr_t x18 asm("x18") = value;
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__asm__ __volatile__("":: [x18]"r"(x18));
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}
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ALWAYS_INLINE void SetExceptionThreadStackTop(uintptr_t top) {
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cpu::SetCntvCvalEl0(top);
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}
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ALWAYS_INLINE void SwitchThreadLocalRegion(uintptr_t tlr) {
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cpu::SetTpidrRoEl0(tlr);
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}
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}
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