mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-11-24 12:52:07 +00:00
225 lines
7.4 KiB
C++
225 lines
7.4 KiB
C++
/*
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* Copyright (c) Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <exosphere.hpp>
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namespace ams::gic {
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namespace {
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struct GicDistributor {
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u32 ctlr;
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u32 typer;
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u32 iidr;
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u32 reserved_0x0c;
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u32 statusr;
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u32 reserved_0x14[3];
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u32 impldef_0x20[8];
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u32 setspi_nsr;
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u32 reserved_0x44;
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u32 clrspi_nsr;
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u32 reserved_0x4c;
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u32 setspi_sr;
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u32 reserved_0x54;
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u32 clrspi_sr;
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u32 reserved_0x5c[9];
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u32 igroupr[32];
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u32 isenabler[32];
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u32 icenabler[32];
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u32 ispendr[32];
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u32 icpendr[32];
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u32 isactiver[32];
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u32 icactiver[32];
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union {
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u8 bytes[1020];
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u32 words[255];
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} ipriorityr;
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u32 _0x7fc;
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union {
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u8 bytes[1020];
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u32 words[255];
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} itargetsr;
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u32 _0xbfc;
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u32 icfgr[64];
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u32 igrpmodr[32];
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u32 _0xd80[32];
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u32 nsacr[64];
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u32 sgir;
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u32 _0xf04[3];
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u32 cpendsgir[4];
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u32 spendsgir[4];
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u32 reserved_0xf30[52];
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static constexpr size_t SgirCpuTargetListShift = 16;
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enum SgirTargetListFilter : u32 {
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SgirTargetListFilter_CpuTargetList = (0 << 24),
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SgirTargetListFilter_Others = (1 << 24),
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SgirTargetListFilter_Self = (2 << 24),
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SgirTargetListFilter_Reserved = (3 << 24),
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};
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};
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static_assert(util::is_pod<GicDistributor>::value);
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static_assert(sizeof(GicDistributor) == 0x1000);
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static_assert(sizeof(GicDistributor) == secmon::MemoryRegionPhysicalDeviceGicDistributor.GetSize());
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struct GicCpuInterface {
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u32 ctlr;
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u32 pmr;
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u32 bpr;
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u32 iar;
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u32 eoir;
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u32 rpr;
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u32 hppir;
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u32 abpr;
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u32 aiar;
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u32 aeoir;
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u32 ahppir;
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u32 statusr;
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u32 reserved_30[4];
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u32 impldef_40[36];
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u32 apr[4];
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u32 nsapr[4];
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u32 reserved_f0[3];
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u32 iidr;
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u32 reserved_100[960];
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u32 dir;
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u32 _0x1004[1023];
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};
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static_assert(util::is_pod<GicCpuInterface>::value);
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static_assert(sizeof(GicCpuInterface) == 0x2000);
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static_assert(sizeof(GicCpuInterface) == secmon::MemoryRegionPhysicalDeviceGicCpuInterface.GetSize());
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constexpr inline int InterruptWords = InterruptCount / BITSIZEOF(u32);
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constexpr inline int SpiIndex = BITSIZEOF(u32);
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constinit uintptr_t g_distributor_address = secmon::MemoryRegionPhysicalDeviceGicDistributor.GetAddress();
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constinit uintptr_t g_cpu_interface_address = secmon::MemoryRegionPhysicalDeviceGicCpuInterface.GetAddress();
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volatile GicDistributor *GetDistributor() {
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return reinterpret_cast<volatile GicDistributor *>(g_distributor_address);
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}
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volatile GicCpuInterface *GetCpuInterface() {
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return reinterpret_cast<volatile GicCpuInterface *>(g_cpu_interface_address);
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}
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void ReadWrite(uintptr_t address, int width, int i, u32 value) {
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/* This code will never be invoked with a negative interrupt id. */
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AMS_ASSUME(i >= 0);
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const int scale = BITSIZEOF(u32) / width;
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const int word = i / scale;
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const int bit = (i % scale) * width;
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const u32 mask = ((1u << width) - 1) << bit;
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const uintptr_t reg_addr = address + sizeof(u32) * word;
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const u32 old = reg::Read(reg_addr) & ~mask;
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reg::Write(reg_addr, old | ((value << bit) & mask));
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}
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void Write(uintptr_t address, int width, int i, u32 value) {
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/* This code will never be invoked with a negative interrupt id. */
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AMS_ASSUME(i >= 0);
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const int scale = BITSIZEOF(u32) / width;
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const int word = i / scale;
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const int bit = (i % scale) * width;
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reg::Write(address + sizeof(u32) * word, value << bit);
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}
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}
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void SetRegisterAddress(uintptr_t distributor_address, uintptr_t cpu_interface_address) {
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g_distributor_address = distributor_address;
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g_cpu_interface_address = cpu_interface_address;
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}
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void InitializeCommon() {
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/* Get the gicd registers. */
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auto *gicd = GetDistributor();
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/* Set IGROUPR for to be FFs. */
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for (int i = SpiIndex / BITSIZEOF(u32); i < InterruptWords; ++i) {
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gicd->igroupr[i] = 0xFFFFFFFFu;
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}
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/* Set IPRIORITYR for spi interrupts to be 0x80. */
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for (int i = SpiIndex; i < InterruptCount; ++i) {
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gicd->ipriorityr.bytes[i] = 0x80;
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}
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/* Enable group 0. */
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gicd->ctlr = 1;
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}
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void InitializeCoreUnique() {
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/* Get the registers. */
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auto *gicd = GetDistributor();
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auto *gicc = GetCpuInterface();
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/* Set IGROUPR0 to be FFs. */
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gicd->igroupr[0] = 0xFFFFFFFFu;
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/* Set IPRIORITYR for core local interrupts to be 0x80. */
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for (int i = 0; i < SpiIndex; ++i) {
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gicd->ipriorityr.bytes[i] = 0x80;
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}
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/* Enable group 0 as FIQs. */
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gicc->ctlr = 0x1D9;
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/* Set PMR. */
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gicc->pmr = 0x80;
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/* Set BPR. */
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gicc->bpr = 7;
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}
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void SetPriority(int interrupt_id, int priority) {
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ReadWrite(g_distributor_address + AMS_OFFSETOF(GicDistributor, ipriorityr), BITSIZEOF(u8), interrupt_id, priority);
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}
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void SetInterruptGroup(int interrupt_id, int group) {
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ReadWrite(g_distributor_address + AMS_OFFSETOF(GicDistributor, igroupr), 1, interrupt_id, group);
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}
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void SetEnable(int interrupt_id, bool enable) {
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Write(g_distributor_address + AMS_OFFSETOF(GicDistributor, isenabler), 1, interrupt_id, enable);
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}
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void SetSpiTargetCpu(int interrupt_id, u32 cpu_mask) {
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ReadWrite(g_distributor_address + AMS_OFFSETOF(GicDistributor, itargetsr), BITSIZEOF(u8), interrupt_id, cpu_mask);
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}
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void SetSpiMode(int interrupt_id, InterruptMode mode) {
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ReadWrite(g_distributor_address + AMS_OFFSETOF(GicDistributor, icfgr), 2, interrupt_id, static_cast<u32>(mode) << 1);
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}
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void SetPending(int interrupt_id) {
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Write(g_distributor_address + AMS_OFFSETOF(GicDistributor, ispendr), 1, interrupt_id, 1);
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}
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int GetInterruptRequestId() {
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return reg::Read(GetCpuInterface()->iar);
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}
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void SetEndOfInterrupt(int interrupt_id) {
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reg::Write(GetCpuInterface()->eoir, interrupt_id);
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}
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}
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