mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
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f66b41c027
exo2: Implement uncompressor stub and boot code up to Main(). exo2: implement some more init (uart/gic) exo2: implement more of init exo2: improve reg api, add keyslot flag setters exo2: implement se aes decryption/enc exo2: fix bugs in loader stub/mmu mappings exo2: start skeletoning bootconfig/global context types arch: fix makefile flags exo2: implement through master key derivation exo2: implement device master keygen exo2: more init through start of SetupSocSecurity exo2: implement pmc secure scratch management se: implement sticky bit validation libexosphere: fix building for arm32 libexo: fix makefile flags libexo: support building for arm64/arm sc7fw: skeleton binary sc7fw: skeleton a little more sc7fw: implement all non-dram functionality exo2: fix DivideUp error sc7fw: implement more dram code, fix reg library errors sc7fw: complete sc7fw impl. exo2: skeleton the rest of SetupSocSecurity exo2: implement fiq interrupt handler exo2: implement all exception handlers exo2: skeleton the entire smc api, implement the svc invoker exo2: implement rest of SetupSocSecurity exo2: correct slave security errors exo2: fix register definition exo2: minor fixes
182 lines
9.1 KiB
C++
182 lines
9.1 KiB
C++
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <exosphere.hpp>
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#include "sc7fw_util.hpp"
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#include "sc7fw_dram.hpp"
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namespace ams::sc7fw {
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namespace {
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constexpr inline const uintptr_t PMC = secmon::MemoryRegionPhysicalDevicePmc.GetAddress();
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void UpdateEmcTiming() {
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/* Enable timing update. */
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reg::Write(EMC_ADDRESS(EMC_TIMING_CONTROL), EMC_REG_BITS_ENUM(TIMING_CONTROL_TIMING_UPDATE, ENABLED));
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/* Wait for the timing update to complete. */
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while (!reg::HasValue(EMC_ADDRESS(EMC_EMC_STATUS), EMC_REG_BITS_ENUM(EMC_STATUS_TIMING_UPDATE_STALLED, DONE))) {
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/* ... */
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}
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}
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void RequestAllPadsPowerDown(uintptr_t addr, uintptr_t expected) {
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constexpr u32 DpdAllRequestValue = reg::Encode(PMC_REG_BITS_ENUM(IO_DPD_REQ_CODE, DPD_ON)) | 0x0FFFFFFF;
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const auto RequestAddress = addr;
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const auto StatusAddress = addr + 4;
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/* Request all pads enter power down. */
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reg::Write(PMC + RequestAddress, DpdAllRequestValue);
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/* Wait until the status reflects our expectation (and all pads are shut down). */
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while (reg::Read(PMC + StatusAddress) != expected) { /* ... */ }
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/* Wait a little while to allow the power down status to propagate. */
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SpinLoop(0x20);
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};
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}
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void SaveEmcFsp() {
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/* We require that the RAM is LPDDR4. */
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AMS_ABORT_UNLESS(reg::HasValue(EMC_ADDRESS(EMC_FBIO_CFG5), EMC_REG_BITS_ENUM(FBIO_CFG5_DRAM_TYPE, LPDDR4)));
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/* Read the frequency set points from MRW3. */
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constexpr u32 FspShift = 6;
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constexpr u32 FspBits = 2;
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constexpr u32 FspMask = ((1u << FspBits) - 1) << FspShift;
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static_assert(FspMask == 0x000000C0);
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const u32 fsp = (reg::Read(EMC_ADDRESS(EMC_MRW3)) & FspMask) >> FspShift;
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/* Write the fsp to PMC_SCRATCH18, where it will be restored to MRW3 by brom. */
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reg::ReadWrite(PMC + APBDEV_PMC_SCRATCH18, REG_BITS_VALUE(FspShift, FspBits, fsp));
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/* Write the fsp twice to PMC_SCRATCH12, where it will be restored to MRW12 by brom. */
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reg::ReadWrite(PMC + APBDEV_PMC_SCRATCH12, REG_BITS_VALUE(FspShift, FspBits, fsp), REG_BITS_VALUE(FspShift + 8, FspBits, fsp));
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/* Write the fsp twice to PMC_SCRATCH13, where it will be restored to MRW13 by brom. */
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reg::ReadWrite(PMC + APBDEV_PMC_SCRATCH13, REG_BITS_VALUE(FspShift, FspBits, fsp), REG_BITS_VALUE(FspShift + 8, FspBits, fsp));
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}
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void EnableSdramSelfRefresh() {
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/* We require that the RAM is dual-channel. */
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AMS_ABORT_UNLESS(reg::HasValue(EMC_ADDRESS(EMC_FBIO_CFG7), EMC_REG_BITS_ENUM(FBIO_CFG7_CH1_ENABLE, ENABLE)));
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/* Disable RAM's ability to dynamically self-refresh, and to opportunistically perform powerdown. */
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reg::Write(EMC_ADDRESS(EMC_CFG), EMC_REG_BITS_ENUM(CFG_DYN_SELF_REF, DISABLED),
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EMC_REG_BITS_ENUM(CFG_DRAM_ACPD, NO_POWERDOWN));
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/* Update the EMC timing. */
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UpdateEmcTiming();
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/* Wait five microseconds. */
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util::WaitMicroSeconds(5);
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/* Disable ZQ calibration. */
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reg::Write(EMC_ADDRESS(EMC_ZCAL_INTERVAL), 0);
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/* Disable automatic calibration. */
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reg::Write(EMC_ADDRESS(EMC_AUTO_CAL_CONFIG), EMC_REG_BITS_ENUM(AUTO_CAL_CONFIG_AUTO_CAL_MEASURE_STALL, ENABLE),
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EMC_REG_BITS_ENUM(AUTO_CAL_CONFIG_AUTO_CAL_UPDATE_STALL, ENABLE),
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EMC_REG_BITS_ENUM(AUTO_CAL_CONFIG_AUTO_CAL_START, DISABLE));
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/* Get whether digital delay locked loops are enabled. */
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const bool has_dll = reg::HasValue(EMC_ADDRESS(EMC_CFG_DIG_DLL), EMC_REG_BITS_ENUM(CFG_DIG_DLL_CFG_DLL_EN, ENABLED));
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if (has_dll) {
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/* If they are, disable them. */
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reg::ReadWrite(EMC_ADDRESS(EMC_CFG_DIG_DLL), EMC_REG_BITS_ENUM(CFG_DIG_DLL_CFG_DLL_EN, DISABLED));
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}
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/* Update the EMC timing. */
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UpdateEmcTiming();
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/* If dll was enabled, wait until both EMC0 and EMC1 have dll disabled. */
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if (has_dll) {
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while (!reg::HasValue(EMC0_ADDRESS(EMC_CFG_DIG_DLL), EMC_REG_BITS_ENUM(CFG_DIG_DLL_CFG_DLL_EN, DISABLED))) { /* ... */ }
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while (!reg::HasValue(EMC1_ADDRESS(EMC_CFG_DIG_DLL), EMC_REG_BITS_ENUM(CFG_DIG_DLL_CFG_DLL_EN, DISABLED))) { /* ... */ }
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}
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/* Stall all reads and writes. */
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reg::Write(EMC_ADDRESS(EMC_REQ_CTRL), EMC_REG_BITS_VALUE(REQ_CTRL_STALL_ALL_READS, 1),
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EMC_REG_BITS_VALUE(REQ_CTRL_STALL_ALL_WRITES, 1));
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/* Wait until both EMC0 and EMC1 have no outstanding transactions. */
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while (!reg::HasValue(EMC0_ADDRESS(EMC_EMC_STATUS), EMC_REG_BITS_ENUM(EMC_STATUS_NO_OUTSTANDING_TRANSACTIONS, COMPLETED))) { /* ... */ }
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while (!reg::HasValue(EMC1_ADDRESS(EMC_EMC_STATUS), EMC_REG_BITS_ENUM(EMC_STATUS_NO_OUTSTANDING_TRANSACTIONS, COMPLETED))) { /* ... */ }
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/* Enable self-refresh. */
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reg::Write(EMC_ADDRESS(EMC_SELF_REF), EMC_REG_BITS_ENUM(SELF_REF_SREF_DEV_SELECTN, BOTH),
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EMC_REG_BITS_ENUM(SELF_REF_SELF_REF_CMD, ENABLED));
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/* Wait until both EMC and EMC1 are in self-refresh. */
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const auto desired = reg::HasValue(EMC_ADDRESS(EMC_ADR_CFG), EMC_REG_BITS_ENUM(ADR_CFG_EMEM_NUMDEV, N2)) ? EMC_REG_BITS_ENUM(EMC_STATUS_DRAM_IN_SELF_REFRESH, BOTH_ENABLED)
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: EMC_REG_BITS_ENUM(EMC_STATUS_DRAM_DEV0_IN_SELF_REFRESH, ENABLED);
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/* NOTE: Nintendo's sc7 entry firmware has a bug here. */
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/* Instead of waiting for both EMCs to report self-refresh, they just read the EMC_STATUS for each EMC. */
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/* This is incorrect, per documentation. */
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while (!reg::HasValue(EMC0_ADDRESS(EMC_EMC_STATUS), desired)) { /* ... */ }
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while (!reg::HasValue(EMC1_ADDRESS(EMC_EMC_STATUS), desired)) { /* ... */ }
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}
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void EnableEmcAllSegmentsRefresh() {
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constexpr int MR17_PASR_Segment = 17;
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/* Write zeros to MR17_PASR_Segment to enable refresh for all segments for dev0. */
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reg::Write(EMC_ADDRESS(EMC_MRW), EMC_REG_BITS_ENUM (MRW_DEV_SELECTN, DEV0),
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EMC_REG_BITS_ENUM (MRW_CNT, EXT1),
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EMC_REG_BITS_VALUE(MRW_MA, MR17_PASR_Segment),
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EMC_REG_BITS_VALUE(MRW_OP, 0));
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/* If dev1 exists, do the same for dev1. */
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if (reg::HasValue(EMC_ADDRESS(EMC_ADR_CFG), EMC_REG_BITS_ENUM(ADR_CFG_EMEM_NUMDEV, N2))) {
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reg::Write(EMC_ADDRESS(EMC_MRW), EMC_REG_BITS_ENUM (MRW_DEV_SELECTN, DEV1),
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EMC_REG_BITS_ENUM (MRW_CNT, EXT1),
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EMC_REG_BITS_VALUE(MRW_MA, MR17_PASR_Segment),
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EMC_REG_BITS_VALUE(MRW_OP, 0));
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}
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}
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void EnableDdrDeepPowerDown() {
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/* Read and decode the parameters Nintendo stores in EMC_PMC_SCRATCH3. */
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const u32 scratch3 = reg::Read(EMC_ADDRESS(EMC_PMC_SCRATCH3));
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const bool weak_bias = (scratch3 & reg::EncodeMask(EMC_REG_BITS_MASK(PMC_SCRATCH3_WEAK_BIAS))) == reg::EncodeValue(EMC_REG_BITS_ENUM(PMC_SCRATCH3_WEAK_BIAS, ENABLED));
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const u32 ddr_cntrl = (scratch3 & reg::EncodeMask(EMC_REG_BITS_MASK(PMC_SCRATCH3_DDR_CNTRL)));
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/* Write the decoded value to PMC_DDR_CNTRL. */
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reg::Write(PMC + APBDEV_PMC_DDR_CNTRL, ddr_cntrl);
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/* If weak bias is enabled, set all VTT_E_WB bits in APBDEV_PMC_WEAK_BIAS. */
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if (weak_bias) {
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constexpr u32 WeakBiasVttEWbAll = 0x7FFF0000;
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reg::Write(PMC + APBDEV_PMC_WEAK_BIAS, WeakBiasVttEWbAll);
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}
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/* Request that DPD3 pads power down. */
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constexpr u32 EristaDpd3Mask = 0x0FFFFFFF;
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constexpr u32 MarikoDpd3Mask = 0x0FFF9FFF;
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if (true /* TODO: IsErista */) {
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RequestAllPadsPowerDown(APBDEV_PMC_IO_DPD3_REQ, EristaDpd3Mask);
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} else {
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RequestAllPadsPowerDown(APBDEV_PMC_IO_DPD3_REQ, MarikoDpd3Mask);
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}
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/* Request that DPD4 pads power down. */
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constexpr u32 Dpd4Mask = 0x0FFF1FFF;
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RequestAllPadsPowerDown(APBDEV_PMC_IO_DPD4_REQ, Dpd4Mask);
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}
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}
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