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https://github.com/Atmosphere-NX/Atmosphere.git
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253 lines
No EOL
11 KiB
C++
253 lines
No EOL
11 KiB
C++
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <exosphere.hpp>
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namespace ams::hw::arch::arm {
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#ifdef __BPMP__
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namespace {
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constexpr inline uintptr_t AVP_CACHE = AVP_CACHE_ADDR(0);
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ALWAYS_INLINE bool IsLargeBuffer(size_t size) {
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/* From TRM: For very large physical buffers or when the full cache needs to be cleared, */
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/* software should simply loop over all lines in all ways and run the *_LINE command on each of them. */
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return size >= DataCacheSize / 4;
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}
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ALWAYS_INLINE bool IsCacheEnabled() {
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return reg::HasValue(AVP_CACHE + AVP_CACHE_CONFIG, AVP_CACHE_REG_BITS_ENUM(CONFIG_ENABLE_CACHE, TRUE));
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}
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void DoPhyCacheOperation(AVP_CACHE_MAINT_OPCODE op, uintptr_t addr) {
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/* Clear maintenance done. */
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reg::Write(AVP_CACHE + AVP_CACHE_INT_CLEAR, AVP_CACHE_REG_BITS_ENUM(INT_CLEAR_MAINTENANCE_DONE, TRUE));
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/* Write maintenance address. */
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reg::Write(AVP_CACHE + AVP_CACHE_MAINT_0, addr);
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/* Write maintenance request. */
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reg::Write(AVP_CACHE + AVP_CACHE_MAINT_2, AVP_CACHE_REG_BITS_VALUE(MAINT_2_WAY_BITMAP, 0x0),
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AVP_CACHE_REG_BITS_VALUE(MAINT_2_OPCODE, op));
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/* Wait for maintenance to be done. */
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while (!reg::HasValue(AVP_CACHE + AVP_CACHE_INT_RAW_EVENT, AVP_CACHE_REG_BITS_ENUM(INT_RAW_EVENT_MAINTENANCE_DONE, TRUE))) {
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/* ... */
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}
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/* Clear raw event. */
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reg::Write(AVP_CACHE + AVP_CACHE_INT_CLEAR, reg::Read(AVP_CACHE + AVP_CACHE_INT_RAW_EVENT));
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}
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void DoEntireCacheOperation(AVP_CACHE_MAINT_OPCODE op) {
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/* Clear maintenance done. */
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reg::Write(AVP_CACHE + AVP_CACHE_INT_CLEAR, AVP_CACHE_REG_BITS_ENUM(INT_CLEAR_MAINTENANCE_DONE, TRUE));
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/* Write maintenance request. */
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reg::Write(AVP_CACHE + AVP_CACHE_MAINT_2, AVP_CACHE_REG_BITS_VALUE(MAINT_2_WAY_BITMAP, 0xF),
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AVP_CACHE_REG_BITS_VALUE(MAINT_2_OPCODE, op));
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/* Wait for maintenance to be done. */
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while (!reg::HasValue(AVP_CACHE + AVP_CACHE_INT_RAW_EVENT, AVP_CACHE_REG_BITS_ENUM(INT_RAW_EVENT_MAINTENANCE_DONE, TRUE))) {
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/* ... */
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}
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/* Clear raw event. */
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reg::Write(AVP_CACHE + AVP_CACHE_INT_CLEAR, reg::Read(AVP_CACHE + AVP_CACHE_INT_RAW_EVENT));
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}
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}
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#define REQUIRE_CACHE_ENABLED() \
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do { \
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if (AMS_UNLIKELY(!IsCacheEnabled())) { \
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return; \
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} \
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} while (false) \
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#define REQUIRE_CACHE_DISABLED() \
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do { \
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if (AMS_UNLIKELY(IsCacheEnabled())) { \
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return; \
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} \
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} while (false) \
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void InitializeDataCache() {
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REQUIRE_CACHE_DISABLED();
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/* Issue init mmu command. */
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reg::Write(AVP_CACHE + AVP_CACHE_MMU_CMD, AVP_CACHE_REG_BITS_ENUM(MMU_CMD_CMD, INIT));
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/* Set mmu fallback entry as RWX, uncached. */
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reg::Write(AVP_CACHE + AVP_CACHE_MMU_FALLBACK_ENTRY, AVP_CACHE_REG_BITS_ENUM(MMU_FALLBACK_ENTRY_WR_ENA, ENABLE),
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AVP_CACHE_REG_BITS_ENUM(MMU_FALLBACK_ENTRY_RD_ENA, ENABLE),
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AVP_CACHE_REG_BITS_ENUM(MMU_FALLBACK_ENTRY_EXE_ENA, ENABLE),
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AVP_CACHE_REG_BITS_ENUM(MMU_FALLBACK_ENTRY_CACHED, DISABLE));
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/* Set mmu cfg. */
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reg::Write(AVP_CACHE + AVP_CACHE_MMU_CFG, AVP_CACHE_REG_BITS_ENUM(MMU_CFG_CLR_ABORT, NOP),
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AVP_CACHE_REG_BITS_ENUM(MMU_CFG_ABORT_MODE, STORE_LAST),
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AVP_CACHE_REG_BITS_ENUM(MMU_CFG_SEQ_CHECK_ALL_ENTRIES, DISABLE),
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AVP_CACHE_REG_BITS_ENUM(MMU_CFG_TLB_ENA, ENABLE),
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AVP_CACHE_REG_BITS_ENUM(MMU_CFG_SEQ_ENA, ENABLE),
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AVP_CACHE_REG_BITS_ENUM(MMU_CFG_BLOCK_MAIN_ENTRY_WR, DISABLE));
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/* Initialize mmu entries. */
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{
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/* Clear shadow copy mask. */
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reg::Write(AVP_CACHE + AVP_CACHE_MMU_SHADOW_COPY_MASK_0, 0);
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/* Add DRAM as index 0, RWX/Cached. */
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{
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reg::Write(AVP_CACHE + AVP_CACHE_MMU_SHADOW_ENTRY_0_MIN_ADDR, 0x80000000);
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reg::Write(AVP_CACHE + AVP_CACHE_MMU_SHADOW_ENTRY_0_MAX_ADDR, util::AlignDown(0xFFFFFFFF, DataCacheLineSize));
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reg::Write(AVP_CACHE + AVP_CACHE_MMU_SHADOW_ENTRY_0_CFG, AVP_CACHE_REG_BITS_ENUM(SHADOW_ENTRY_CFG_WR_ENA, ENABLE),
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AVP_CACHE_REG_BITS_ENUM(SHADOW_ENTRY_CFG_RD_ENA, ENABLE),
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AVP_CACHE_REG_BITS_ENUM(SHADOW_ENTRY_CFG_EXE_ENA, ENABLE),
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AVP_CACHE_REG_BITS_ENUM(SHADOW_ENTRY_CFG_CACHED, ENABLE));
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reg::SetBits(AVP_CACHE + AVP_CACHE_MMU_SHADOW_COPY_MASK_0, (1 << 0));
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}
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/* Add IRAM as index 1, RWX/Cached. */
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{
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reg::Write(AVP_CACHE + AVP_CACHE_MMU_SHADOW_ENTRY_1_MIN_ADDR, 0x40000000);
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reg::Write(AVP_CACHE + AVP_CACHE_MMU_SHADOW_ENTRY_1_MAX_ADDR, util::AlignDown(0x4003FFFF, DataCacheLineSize));
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reg::Write(AVP_CACHE + AVP_CACHE_MMU_SHADOW_ENTRY_1_CFG, AVP_CACHE_REG_BITS_ENUM(SHADOW_ENTRY_CFG_WR_ENA, ENABLE),
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AVP_CACHE_REG_BITS_ENUM(SHADOW_ENTRY_CFG_RD_ENA, ENABLE),
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AVP_CACHE_REG_BITS_ENUM(SHADOW_ENTRY_CFG_EXE_ENA, ENABLE),
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AVP_CACHE_REG_BITS_ENUM(SHADOW_ENTRY_CFG_CACHED, ENABLE));
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reg::SetBits(AVP_CACHE + AVP_CACHE_MMU_SHADOW_COPY_MASK_0, (1 << 1));
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}
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/* Issue copy shadow mmu command. */
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reg::Write(AVP_CACHE + AVP_CACHE_MMU_CMD, AVP_CACHE_REG_BITS_ENUM(MMU_CMD_CMD, COPY_SHADOW));
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}
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/* Invalidate entire cache. */
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DoEntireCacheOperation(AVP_CACHE_MAINT_OPCODE_INVALID_WAY);
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/* Enable the cache. */
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reg::Write(AVP_CACHE + AVP_CACHE_CONFIG, AVP_CACHE_REG_BITS_ENUM(CONFIG_ENABLE_CACHE, TRUE),
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AVP_CACHE_REG_BITS_ENUM(CONFIG_FORCE_WRITE_THROUGH, TRUE),
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AVP_CACHE_REG_BITS_ENUM(CONFIG_MMU_TAG_MODE, PARALLEL),
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AVP_CACHE_REG_BITS_ENUM(CONFIG_TAG_CHECK_ABORT_ON_ERROR, TRUE));
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/* Invalidate entire cache again (WAR for hardware bug). */
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DoEntireCacheOperation(AVP_CACHE_MAINT_OPCODE_INVALID_WAY);
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}
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void FinalizeDataCache() {
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REQUIRE_CACHE_ENABLED();
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/* Flush entire data cache. */
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FlushEntireDataCache();
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/* Disable cache. */
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reg::Write(AVP_CACHE + AVP_CACHE_CONFIG, AVP_CACHE_REG_BITS_ENUM(CONFIG_ENABLE_CACHE, FALSE));
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}
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void InvalidateEntireDataCache() {
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REQUIRE_CACHE_ENABLED();
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DoEntireCacheOperation(AVP_CACHE_MAINT_OPCODE_INVALID_WAY);
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}
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void StoreEntireDataCache() {
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REQUIRE_CACHE_ENABLED();
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DoEntireCacheOperation(AVP_CACHE_MAINT_OPCODE_CLEAN_WAY);
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}
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void FlushEntireDataCache() {
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REQUIRE_CACHE_ENABLED();
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DoEntireCacheOperation(AVP_CACHE_MAINT_OPCODE_CLEAN_INVALID_WAY);
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}
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void InvalidateDataCacheLine(void *ptr) {
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/* NOTE: Don't check cache enabled as an optimization, as only direct caller will be InvalidateDataCache(). */
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/* REQUIRE_CACHE_ENABLED(); */
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DoPhyCacheOperation(AVP_CACHE_MAINT_OPCODE_INVALID_PHY, reinterpret_cast<uintptr_t>(ptr));
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}
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void StoreDataCacheLine(void *ptr) {
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/* NOTE: Don't check cache enabled as an optimization, as only direct caller will be FlushDataCache(). */
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/* REQUIRE_CACHE_ENABLED(); */
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DoPhyCacheOperation(AVP_CACHE_MAINT_OPCODE_CLEAN_PHY, reinterpret_cast<uintptr_t>(ptr));
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}
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void FlushDataCacheLine(void *ptr) {
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/* NOTE: Don't check cache enabled as an optimization, as only direct caller will be FlushDataCache(). */
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/* REQUIRE_CACHE_ENABLED(); */
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DoPhyCacheOperation(AVP_CACHE_MAINT_OPCODE_CLEAN_INVALID_PHY, reinterpret_cast<uintptr_t>(ptr));
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}
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void InvalidateDataCache(void *ptr, size_t size) {
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REQUIRE_CACHE_ENABLED();
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if (IsLargeBuffer(size)) {
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InvalidateEntireDataCache();
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} else {
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const uintptr_t start = reinterpret_cast<uintptr_t>(ptr);
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const uintptr_t end = util::AlignUp(start + size, hw::DataCacheLineSize);
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for (uintptr_t cur = start; cur < end; cur += hw::DataCacheLineSize) {
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InvalidateDataCacheLine(reinterpret_cast<void *>(cur));
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}
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}
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}
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void StoreDataCache(const void *ptr, size_t size) {
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REQUIRE_CACHE_ENABLED();
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if (IsLargeBuffer(size)) {
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StoreEntireDataCache();
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} else {
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const uintptr_t start = reinterpret_cast<uintptr_t>(ptr);
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const uintptr_t end = util::AlignUp(start + size, hw::DataCacheLineSize);
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for (uintptr_t cur = start; cur < end; cur += hw::DataCacheLineSize) {
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StoreDataCacheLine(reinterpret_cast<void *>(cur));
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}
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}
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}
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void FlushDataCache(const void *ptr, size_t size) {
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REQUIRE_CACHE_ENABLED();
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if (IsLargeBuffer(size)) {
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FlushEntireDataCache();
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} else {
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const uintptr_t start = reinterpret_cast<uintptr_t>(ptr);
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const uintptr_t end = util::AlignUp(start + size, hw::DataCacheLineSize);
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for (uintptr_t cur = start; cur < end; cur += hw::DataCacheLineSize) {
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FlushDataCacheLine(reinterpret_cast<void *>(cur));
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}
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}
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}
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#endif
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} |