2019-03-15 03:37:54 +00:00
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using Ryujinx.Common.Logging;
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2020-05-03 23:54:50 +01:00
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using Ryujinx.Cpu;
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2018-12-18 05:33:36 +00:00
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using Ryujinx.HLE.HOS.Kernel.Common;
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using Ryujinx.HLE.HOS.Kernel.Process;
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2022-01-29 21:18:03 +00:00
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using Ryujinx.HLE.HOS.Kernel.SupervisorCall;
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2018-09-19 00:36:43 +01:00
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using System;
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2018-05-14 07:01:10 +01:00
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using System.Collections.Generic;
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2020-12-09 22:20:05 +00:00
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using System.Numerics;
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Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 19:56:22 +01:00
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using System.Threading;
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2018-09-19 00:36:43 +01:00
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2018-12-18 05:33:36 +00:00
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namespace Ryujinx.HLE.HOS.Kernel.Threading
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2018-02-04 23:08:20 +00:00
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{
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2018-09-19 00:36:43 +01:00
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class KThread : KSynchronizationObject, IKFutureSchedulerObject
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2018-02-04 23:08:20 +00:00
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{
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2021-12-30 09:55:06 +00:00
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private const int TlsUserDisableCountOffset = 0x100;
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private const int TlsUserInterruptFlagOffset = 0x102;
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2020-07-17 05:22:13 +01:00
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public const int MaxWaitSyncObjects = 64;
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2020-12-09 22:20:05 +00:00
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private ManualResetEvent _schedulerWaitEvent;
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public ManualResetEvent SchedulerWaitEvent => _schedulerWaitEvent;
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Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 19:56:22 +01:00
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public Thread HostThread { get; private set; }
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2019-10-31 18:09:03 +00:00
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public ARMeilleure.State.ExecutionContext Context { get; private set; }
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2018-02-04 23:08:20 +00:00
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2020-12-09 22:20:05 +00:00
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public KThreadContext ThreadContext { get; private set; }
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public int DynamicPriority { get; set; }
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2022-01-29 21:18:03 +00:00
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public ulong AffinityMask { get; set; }
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2018-05-13 04:22:42 +01:00
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2022-02-09 20:18:07 +00:00
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public ulong ThreadUid { get; private set; }
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2018-04-21 20:07:16 +01:00
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2020-12-09 22:20:05 +00:00
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private long _totalTimeRunning;
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public long TotalTimeRunning => _totalTimeRunning;
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2018-11-28 22:18:09 +00:00
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public KSynchronizationObject SignaledObj { get; set; }
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2018-05-16 02:36:08 +01:00
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2018-12-18 05:33:36 +00:00
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public ulong CondVarAddress { get; set; }
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2018-05-13 04:22:42 +01:00
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2018-12-06 11:16:24 +00:00
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private ulong _entrypoint;
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2020-12-01 23:23:43 +00:00
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private ThreadStart _customThreadStart;
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2020-12-09 22:20:05 +00:00
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private bool _forcedUnschedulable;
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public bool IsSchedulable => _customThreadStart == null && !_forcedUnschedulable;
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2018-11-28 22:18:09 +00:00
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2018-12-18 05:33:36 +00:00
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public ulong MutexAddress { get; set; }
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2021-12-30 09:55:06 +00:00
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public int KernelWaitersCount { get; private set; }
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2018-11-28 22:18:09 +00:00
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public KProcess Owner { get; private set; }
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2018-04-21 20:07:16 +01:00
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2018-12-06 11:16:24 +00:00
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private ulong _tlsAddress;
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2018-11-28 22:18:09 +00:00
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2019-01-18 22:26:39 +00:00
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public ulong TlsAddress => _tlsAddress;
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2020-07-17 05:22:13 +01:00
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public KSynchronizationObject[] WaitSyncObjects { get; }
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public int[] WaitSyncHandles { get; }
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2018-11-28 22:18:09 +00:00
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public long LastScheduledTime { get; set; }
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2018-04-21 20:07:16 +01:00
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2018-12-05 00:52:39 +00:00
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public LinkedListNode<KThread>[] SiblingsPerCore { get; private set; }
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2018-04-21 20:07:16 +01:00
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2020-12-01 23:23:43 +00:00
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public LinkedList<KThread> Withholder { get; set; }
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2018-11-28 22:18:09 +00:00
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public LinkedListNode<KThread> WithholderNode { get; set; }
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public LinkedListNode<KThread> ProcessListNode { get; set; }
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2018-04-19 03:52:23 +01:00
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2020-12-01 23:23:43 +00:00
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private LinkedList<KThread> _mutexWaiters;
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2018-12-06 11:16:24 +00:00
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private LinkedListNode<KThread> _mutexWaiterNode;
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2018-02-14 02:43:08 +00:00
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2021-12-30 09:55:06 +00:00
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private LinkedList<KThread> _pinnedWaiters;
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2018-09-19 00:36:43 +01:00
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public KThread MutexOwner { get; private set; }
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2018-06-26 05:09:32 +01:00
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2018-09-19 00:36:43 +01:00
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public int ThreadHandleForUserMutex { get; set; }
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2018-12-06 11:16:24 +00:00
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private ThreadSchedState _forcePauseFlags;
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2021-12-30 09:55:06 +00:00
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private ThreadSchedState _forcePausePermissionFlags;
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2018-09-19 00:36:43 +01:00
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2018-12-18 05:33:36 +00:00
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public KernelResult ObjSyncResult { get; set; }
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2018-09-19 00:36:43 +01:00
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2020-12-01 23:23:43 +00:00
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public int BasePriority { get; set; }
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public int PreferredCore { get; set; }
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2018-09-19 00:36:43 +01:00
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2020-12-09 22:20:05 +00:00
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public int CurrentCore { get; set; }
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public int ActiveCore { get; set; }
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2021-12-30 09:55:06 +00:00
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public bool IsPinned { get; private set; }
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2022-01-29 21:18:03 +00:00
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private ulong _originalAffinityMask;
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2021-12-30 09:55:06 +00:00
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private int _originalPreferredCore;
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private int _originalBasePriority;
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private int _coreMigrationDisableCount;
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2018-09-19 00:36:43 +01:00
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public ThreadSchedState SchedFlags { get; private set; }
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2019-12-26 01:50:17 +00:00
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private int _shallBeTerminated;
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2020-12-01 23:23:43 +00:00
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public bool ShallBeTerminated
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{
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get => _shallBeTerminated != 0;
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set => _shallBeTerminated = value ? 1 : 0;
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}
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2018-09-19 00:36:43 +01:00
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2020-12-09 22:20:05 +00:00
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public bool TerminationRequested => ShallBeTerminated || SchedFlags == ThreadSchedState.TerminationPending;
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2018-09-19 00:36:43 +01:00
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public bool SyncCancelled { get; set; }
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2020-12-01 23:23:43 +00:00
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public bool WaitingSync { get; set; }
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2018-09-19 00:36:43 +01:00
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2020-12-09 22:20:05 +00:00
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private int _hasExited;
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2019-01-18 22:26:39 +00:00
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private bool _hasBeenInitialized;
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private bool _hasBeenReleased;
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2018-09-19 00:36:43 +01:00
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public bool WaitingInArbitration { get; set; }
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public long LastPc { get; set; }
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2018-02-14 02:43:08 +00:00
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2021-12-30 09:55:06 +00:00
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private object ActivityOperationLock = new object();
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2020-05-04 04:41:29 +01:00
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public KThread(KernelContext context) : base(context)
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2018-02-04 23:08:20 +00:00
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{
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2020-07-17 05:22:13 +01:00
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WaitSyncObjects = new KSynchronizationObject[MaxWaitSyncObjects];
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WaitSyncHandles = new int[MaxWaitSyncObjects];
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2018-09-19 00:36:43 +01:00
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SiblingsPerCore = new LinkedListNode<KThread>[KScheduler.CpuCoresCount];
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2018-05-14 07:01:10 +01:00
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2018-12-06 11:16:24 +00:00
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_mutexWaiters = new LinkedList<KThread>();
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2021-12-30 09:55:06 +00:00
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_pinnedWaiters = new LinkedList<KThread>();
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2018-11-28 22:18:09 +00:00
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}
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public KernelResult Initialize(
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2020-12-01 23:23:43 +00:00
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ulong entrypoint,
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ulong argsPtr,
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ulong stackTop,
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int priority,
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2020-12-09 22:20:05 +00:00
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int cpuCore,
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2020-12-01 23:23:43 +00:00
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KProcess owner,
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ThreadType type,
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ThreadStart customThreadStart = null)
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2018-11-28 22:18:09 +00:00
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{
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2018-12-06 11:16:24 +00:00
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if ((uint)type > 3)
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2018-11-28 22:18:09 +00:00
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{
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2018-12-06 11:16:24 +00:00
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throw new ArgumentException($"Invalid thread type \"{type}\".");
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2018-11-28 22:18:09 +00:00
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}
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2018-04-21 20:07:16 +01:00
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2020-12-09 22:20:05 +00:00
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ThreadContext = new KThreadContext();
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2018-09-19 00:36:43 +01:00
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2020-12-09 22:20:05 +00:00
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PreferredCore = cpuCore;
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2022-01-29 21:18:03 +00:00
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AffinityMask |= 1UL << cpuCore;
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2018-11-28 22:18:09 +00:00
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2018-12-06 11:16:24 +00:00
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SchedFlags = type == ThreadType.Dummy
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2018-11-28 22:18:09 +00:00
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? ThreadSchedState.Running
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: ThreadSchedState.None;
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2018-09-19 00:36:43 +01:00
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2020-12-09 22:20:05 +00:00
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ActiveCore = cpuCore;
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ObjSyncResult = KernelResult.ThreadNotStarted;
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2018-12-06 11:16:24 +00:00
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DynamicPriority = priority;
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2020-12-01 23:23:43 +00:00
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BasePriority = priority;
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2020-12-09 22:20:05 +00:00
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CurrentCore = cpuCore;
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2021-12-30 09:55:06 +00:00
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IsPinned = false;
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2018-11-28 22:18:09 +00:00
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2018-12-06 11:16:24 +00:00
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_entrypoint = entrypoint;
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2020-12-01 23:23:43 +00:00
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_customThreadStart = customThreadStart;
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2018-11-28 22:18:09 +00:00
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2018-12-06 11:16:24 +00:00
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if (type == ThreadType.User)
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2018-11-28 22:18:09 +00:00
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{
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2018-12-06 11:16:24 +00:00
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if (owner.AllocateThreadLocalStorage(out _tlsAddress) != KernelResult.Success)
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2018-11-28 22:18:09 +00:00
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{
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return KernelResult.OutOfMemory;
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}
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2021-04-24 11:16:01 +01:00
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MemoryHelper.FillWithZeros(owner.CpuMemory, _tlsAddress, KTlsPageInfo.TlsEntrySize);
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2018-11-28 22:18:09 +00:00
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}
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2018-12-06 11:16:24 +00:00
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bool is64Bits;
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2018-11-28 22:18:09 +00:00
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2018-12-06 11:16:24 +00:00
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if (owner != null)
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2018-11-28 22:18:09 +00:00
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{
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2018-12-06 11:16:24 +00:00
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Owner = owner;
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2018-11-28 22:18:09 +00:00
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2019-01-18 22:26:39 +00:00
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owner.IncrementReferenceCount();
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2018-12-06 11:16:24 +00:00
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owner.IncrementThreadCount();
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2018-11-28 22:18:09 +00:00
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|
|
|
2020-12-01 23:23:43 +00:00
|
|
|
is64Bits = owner.Flags.HasFlag(ProcessCreationFlags.Is64Bit);
|
2018-11-28 22:18:09 +00:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2018-12-06 11:16:24 +00:00
|
|
|
is64Bits = true;
|
2018-11-28 22:18:09 +00:00
|
|
|
}
|
|
|
|
|
2020-12-01 23:23:43 +00:00
|
|
|
HostThread = new Thread(ThreadStart);
|
2018-11-28 22:18:09 +00:00
|
|
|
|
2020-05-03 23:54:50 +01:00
|
|
|
Context = CpuContext.CreateExecutionContext();
|
Implement some ARM32 memory instructions and CMP (#565)
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants)
* Rename some opcode classes and flag masks for consistency
* Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations
* Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC
* Re-align arm32 instructions on the opcode table
2019-01-29 16:06:11 +00:00
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
Context.IsAarch32 = !is64Bits;
|
2019-11-14 14:28:13 +00:00
|
|
|
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 19:56:22 +01:00
|
|
|
Context.SetX(0, argsPtr);
|
Implement some ARM32 memory instructions and CMP (#565)
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants)
* Rename some opcode classes and flag masks for consistency
* Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations
* Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC
* Re-align arm32 instructions on the opcode table
2019-01-29 16:06:11 +00:00
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
if (is64Bits)
|
Implement some ARM32 memory instructions and CMP (#565)
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants)
* Rename some opcode classes and flag masks for consistency
* Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations
* Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC
* Re-align arm32 instructions on the opcode table
2019-01-29 16:06:11 +00:00
|
|
|
{
|
2021-11-28 12:01:17 +00:00
|
|
|
Context.SetX(18, KSystemControl.GenerateRandom() | 1);
|
2020-12-09 22:20:05 +00:00
|
|
|
Context.SetX(31, stackTop);
|
Implement some ARM32 memory instructions and CMP (#565)
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants)
* Rename some opcode classes and flag masks for consistency
* Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations
* Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC
* Re-align arm32 instructions on the opcode table
2019-01-29 16:06:11 +00:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
Context.SetX(13, (uint)stackTop);
|
Implement some ARM32 memory instructions and CMP (#565)
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants)
* Rename some opcode classes and flag masks for consistency
* Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations
* Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC
* Re-align arm32 instructions on the opcode table
2019-01-29 16:06:11 +00:00
|
|
|
}
|
2018-11-28 22:18:09 +00:00
|
|
|
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 19:56:22 +01:00
|
|
|
Context.CntfrqEl0 = 19200000;
|
2020-12-01 23:23:43 +00:00
|
|
|
Context.Tpidr = (long)_tlsAddress;
|
2018-11-28 22:18:09 +00:00
|
|
|
|
2020-05-04 04:41:29 +01:00
|
|
|
ThreadUid = KernelContext.NewThreadUid();
|
2018-11-28 22:18:09 +00:00
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
HostThread.Name = customThreadStart != null ? $"HLE.OsThread.{ThreadUid}" : $"HLE.GuestThread.{ThreadUid}";
|
2019-12-26 01:50:17 +00:00
|
|
|
|
2019-01-18 22:26:39 +00:00
|
|
|
_hasBeenInitialized = true;
|
|
|
|
|
2021-12-30 09:55:06 +00:00
|
|
|
_forcePausePermissionFlags = ThreadSchedState.ForcePauseMask;
|
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
if (owner != null)
|
2018-11-28 22:18:09 +00:00
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
owner.SubscribeThreadEventHandlers(Context);
|
2018-12-06 11:16:24 +00:00
|
|
|
owner.AddThread(this);
|
2018-11-28 22:18:09 +00:00
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
if (owner.IsPaused)
|
2018-11-28 22:18:09 +00:00
|
|
|
{
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-11-28 22:18:09 +00:00
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
if (TerminationRequested)
|
2018-11-28 22:18:09 +00:00
|
|
|
{
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-11-28 22:18:09 +00:00
|
|
|
|
|
|
|
return KernelResult.Success;
|
|
|
|
}
|
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
_forcePauseFlags |= ThreadSchedState.ProcessPauseFlag;
|
2018-11-28 22:18:09 +00:00
|
|
|
|
|
|
|
CombineForcePauseFlags();
|
|
|
|
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-11-28 22:18:09 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return KernelResult.Success;
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
|
2018-11-28 22:18:09 +00:00
|
|
|
public KernelResult Start()
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2020-05-04 04:41:29 +01:00
|
|
|
if (!KernelContext.KernelInitialized)
|
2018-11-28 22:18:09 +00:00
|
|
|
{
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-11-28 22:18:09 +00:00
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
if (!TerminationRequested)
|
2018-11-28 22:18:09 +00:00
|
|
|
{
|
2018-12-06 11:16:24 +00:00
|
|
|
_forcePauseFlags |= ThreadSchedState.KernelInitPauseFlag;
|
2018-11-28 22:18:09 +00:00
|
|
|
|
|
|
|
CombineForcePauseFlags();
|
|
|
|
}
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-11-28 22:18:09 +00:00
|
|
|
}
|
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
KernelResult result = KernelResult.ThreadTerminating;
|
2018-11-28 22:18:09 +00:00
|
|
|
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-09-19 00:36:43 +01:00
|
|
|
|
|
|
|
if (!ShallBeTerminated)
|
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
KThread currentThread = KernelStatic.GetCurrentThread();
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
while (SchedFlags != ThreadSchedState.TerminationPending && (currentThread == null || !currentThread.TerminationRequested))
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2018-11-28 22:18:09 +00:00
|
|
|
if ((SchedFlags & ThreadSchedState.LowMask) != ThreadSchedState.None)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2018-12-06 11:16:24 +00:00
|
|
|
result = KernelResult.InvalidState;
|
2018-09-19 00:36:43 +01:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
if (currentThread == null || currentThread._forcePauseFlags == ThreadSchedState.None)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2018-12-06 11:16:24 +00:00
|
|
|
if (Owner != null && _forcePauseFlags != ThreadSchedState.None)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
|
|
|
CombineForcePauseFlags();
|
|
|
|
}
|
|
|
|
|
|
|
|
SetNewSchedFlags(ThreadSchedState.Running);
|
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
StartHostThread();
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
result = KernelResult.Success;
|
2018-09-19 00:36:43 +01:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2018-12-06 11:16:24 +00:00
|
|
|
currentThread.CombineForcePauseFlags();
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Leave();
|
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
if (currentThread.ShallBeTerminated)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
return result;
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
|
2019-12-26 01:50:17 +00:00
|
|
|
public ThreadSchedState PrepareForTermination()
|
|
|
|
{
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2019-12-26 01:50:17 +00:00
|
|
|
|
2021-12-30 09:55:06 +00:00
|
|
|
if (Owner != null && Owner.PinnedThreads[KernelStatic.GetCurrentThread().CurrentCore] == this)
|
|
|
|
{
|
|
|
|
Owner.UnpinThread(this);
|
|
|
|
}
|
|
|
|
|
2019-12-26 01:50:17 +00:00
|
|
|
ThreadSchedState result;
|
|
|
|
|
|
|
|
if (Interlocked.CompareExchange(ref _shallBeTerminated, 1, 0) == 0)
|
|
|
|
{
|
|
|
|
if ((SchedFlags & ThreadSchedState.LowMask) == ThreadSchedState.None)
|
|
|
|
{
|
|
|
|
SchedFlags = ThreadSchedState.TerminationPending;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (_forcePauseFlags != ThreadSchedState.None)
|
|
|
|
{
|
|
|
|
_forcePauseFlags &= ~ThreadSchedState.ThreadPauseFlag;
|
|
|
|
|
|
|
|
ThreadSchedState oldSchedFlags = SchedFlags;
|
|
|
|
|
|
|
|
SchedFlags &= ThreadSchedState.LowMask;
|
|
|
|
|
|
|
|
AdjustScheduling(oldSchedFlags);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (BasePriority >= 0x10)
|
|
|
|
{
|
|
|
|
SetPriority(0xF);
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((SchedFlags & ThreadSchedState.LowMask) == ThreadSchedState.Running)
|
|
|
|
{
|
|
|
|
// TODO: GIC distributor stuffs (sgir changes ect)
|
2020-09-22 05:50:40 +01:00
|
|
|
Context.RequestInterrupt();
|
2019-12-26 01:50:17 +00:00
|
|
|
}
|
|
|
|
|
2020-12-01 23:23:43 +00:00
|
|
|
SignaledObj = null;
|
2019-12-26 01:50:17 +00:00
|
|
|
ObjSyncResult = KernelResult.ThreadTerminating;
|
|
|
|
|
|
|
|
ReleaseAndResume();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
result = SchedFlags;
|
|
|
|
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2019-12-26 01:50:17 +00:00
|
|
|
|
|
|
|
return result & ThreadSchedState.LowMask;
|
|
|
|
}
|
|
|
|
|
|
|
|
public void Terminate()
|
|
|
|
{
|
|
|
|
ThreadSchedState state = PrepareForTermination();
|
|
|
|
|
|
|
|
if (state != ThreadSchedState.TerminationPending)
|
|
|
|
{
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.Synchronization.WaitFor(new KSynchronizationObject[] { this }, -1, out _);
|
2019-12-26 01:50:17 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
public void HandlePostSyscall()
|
|
|
|
{
|
|
|
|
ThreadSchedState state;
|
|
|
|
|
|
|
|
do
|
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
if (TerminationRequested)
|
2019-12-26 01:50:17 +00:00
|
|
|
{
|
|
|
|
Exit();
|
|
|
|
|
|
|
|
// As the death of the thread is handled by the CPU emulator, we differ from the official kernel and return here.
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2019-12-26 01:50:17 +00:00
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
if (TerminationRequested)
|
2019-12-26 01:50:17 +00:00
|
|
|
{
|
|
|
|
state = ThreadSchedState.TerminationPending;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (_forcePauseFlags != ThreadSchedState.None)
|
|
|
|
{
|
|
|
|
CombineForcePauseFlags();
|
|
|
|
}
|
|
|
|
|
|
|
|
state = ThreadSchedState.Running;
|
|
|
|
}
|
|
|
|
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2019-12-26 01:50:17 +00:00
|
|
|
} while (state == ThreadSchedState.TerminationPending);
|
|
|
|
}
|
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
public void Exit()
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
// TODO: Debug event.
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
if (Owner != null)
|
|
|
|
{
|
|
|
|
Owner.ResourceLimit?.Release(LimitableResource.Thread, 0, 1);
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
_hasBeenReleased = true;
|
|
|
|
}
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
_forcePauseFlags &= ~ThreadSchedState.ForcePauseMask;
|
2021-12-30 09:55:06 +00:00
|
|
|
_forcePausePermissionFlags = 0;
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
bool decRef = ExitImpl();
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
Context.StopRunning();
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
if (decRef)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
DecrementReferenceCount();
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
private bool ExitImpl()
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
SetNewSchedFlags(ThreadSchedState.TerminationPending);
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
bool decRef = Interlocked.Exchange(ref _hasExited, 1) == 0;
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
Signal();
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
return decRef;
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
|
2021-12-30 09:55:06 +00:00
|
|
|
private int GetEffectiveRunningCore()
|
|
|
|
{
|
|
|
|
for (int coreNumber = 0; coreNumber < KScheduler.CpuCoresCount; coreNumber++)
|
|
|
|
{
|
|
|
|
if (KernelContext.Schedulers[coreNumber].CurrentThread == this)
|
|
|
|
{
|
|
|
|
return coreNumber;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
public KernelResult Sleep(long timeout)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
if (ShallBeTerminated || SchedFlags == ThreadSchedState.TerminationPending)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
return KernelResult.ThreadTerminating;
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
SetNewSchedFlags(ThreadSchedState.Paused);
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
if (timeout > 0)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
KernelContext.TimeManager.ScheduleFutureInvocation(this, timeout);
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
if (timeout > 0)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
KernelContext.TimeManager.UnscheduleFutureInvocation(this);
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
return 0;
|
2018-04-21 20:07:16 +01:00
|
|
|
}
|
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
public void SetPriority(int priority)
|
2018-04-21 20:07:16 +01:00
|
|
|
{
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-04-21 20:07:16 +01:00
|
|
|
|
2021-12-30 09:55:06 +00:00
|
|
|
if (IsPinned)
|
|
|
|
{
|
|
|
|
_originalBasePriority = priority;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
BasePriority = priority;
|
|
|
|
}
|
2018-09-19 00:36:43 +01:00
|
|
|
|
|
|
|
UpdatePriorityInheritance();
|
|
|
|
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-04-21 20:07:16 +01:00
|
|
|
}
|
|
|
|
|
2021-09-11 21:08:25 +01:00
|
|
|
public void Suspend(ThreadSchedState type)
|
|
|
|
{
|
|
|
|
_forcePauseFlags |= type;
|
|
|
|
|
|
|
|
CombineForcePauseFlags();
|
|
|
|
}
|
|
|
|
|
|
|
|
public void Resume(ThreadSchedState type)
|
|
|
|
{
|
|
|
|
ThreadSchedState oldForcePauseFlags = _forcePauseFlags;
|
|
|
|
|
|
|
|
_forcePauseFlags &= ~type;
|
|
|
|
|
|
|
|
if ((oldForcePauseFlags & ~type) == ThreadSchedState.None)
|
|
|
|
{
|
|
|
|
ThreadSchedState oldSchedFlags = SchedFlags;
|
|
|
|
|
|
|
|
SchedFlags &= ThreadSchedState.LowMask;
|
|
|
|
|
|
|
|
AdjustScheduling(oldSchedFlags);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-12-18 05:33:36 +00:00
|
|
|
public KernelResult SetActivity(bool pause)
|
2018-04-21 20:07:16 +01:00
|
|
|
{
|
2021-12-30 09:55:06 +00:00
|
|
|
lock (ActivityOperationLock)
|
|
|
|
{
|
|
|
|
KernelResult result = KernelResult.Success;
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2021-12-30 09:55:06 +00:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-04-21 20:07:16 +01:00
|
|
|
|
2021-12-30 09:55:06 +00:00
|
|
|
ThreadSchedState lowNibble = SchedFlags & ThreadSchedState.LowMask;
|
2018-06-22 03:05:42 +01:00
|
|
|
|
2021-12-30 09:55:06 +00:00
|
|
|
if (lowNibble != ThreadSchedState.Paused && lowNibble != ThreadSchedState.Running)
|
|
|
|
{
|
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2021-12-30 09:55:06 +00:00
|
|
|
return KernelResult.InvalidState;
|
|
|
|
}
|
2018-06-22 03:05:42 +01:00
|
|
|
|
2021-12-30 09:55:06 +00:00
|
|
|
if (!ShallBeTerminated && SchedFlags != ThreadSchedState.TerminationPending)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2021-12-30 09:55:06 +00:00
|
|
|
if (pause)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2021-12-30 09:55:06 +00:00
|
|
|
// Pause, the force pause flag should be clear (thread is NOT paused).
|
|
|
|
if ((_forcePauseFlags & ThreadSchedState.ThreadPauseFlag) == 0)
|
|
|
|
{
|
|
|
|
Suspend(ThreadSchedState.ThreadPauseFlag);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = KernelResult.InvalidState;
|
|
|
|
}
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2021-12-30 09:55:06 +00:00
|
|
|
// Unpause, the force pause flag should be set (thread is paused).
|
|
|
|
if ((_forcePauseFlags & ThreadSchedState.ThreadPauseFlag) != 0)
|
|
|
|
{
|
|
|
|
Resume(ThreadSchedState.ThreadPauseFlag);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = KernelResult.InvalidState;
|
|
|
|
}
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
}
|
2021-12-30 09:55:06 +00:00
|
|
|
|
|
|
|
KernelContext.CriticalSection.Leave();
|
|
|
|
|
|
|
|
if (result == KernelResult.Success && pause)
|
2018-04-21 20:07:16 +01:00
|
|
|
{
|
2021-12-30 09:55:06 +00:00
|
|
|
bool isThreadRunning = true;
|
|
|
|
|
|
|
|
while (isThreadRunning)
|
2018-05-13 04:22:42 +01:00
|
|
|
{
|
2021-12-30 09:55:06 +00:00
|
|
|
KernelContext.CriticalSection.Enter();
|
|
|
|
|
|
|
|
if (TerminationRequested)
|
|
|
|
{
|
|
|
|
KernelContext.CriticalSection.Leave();
|
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
isThreadRunning = false;
|
|
|
|
|
|
|
|
if (IsPinned)
|
|
|
|
{
|
|
|
|
KThread currentThread = KernelStatic.GetCurrentThread();
|
|
|
|
|
|
|
|
if (currentThread.TerminationRequested)
|
|
|
|
{
|
|
|
|
KernelContext.CriticalSection.Leave();
|
|
|
|
|
|
|
|
result = KernelResult.ThreadTerminating;
|
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
_pinnedWaiters.AddLast(currentThread);
|
|
|
|
|
|
|
|
currentThread.Reschedule(ThreadSchedState.Paused);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
isThreadRunning = GetEffectiveRunningCore() >= 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-05-13 04:22:42 +01:00
|
|
|
}
|
|
|
|
}
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2021-12-30 09:55:06 +00:00
|
|
|
return result;
|
|
|
|
}
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
|
2022-01-29 21:18:03 +00:00
|
|
|
public KernelResult GetThreadContext3(out ThreadContext context)
|
|
|
|
{
|
|
|
|
context = default;
|
|
|
|
|
|
|
|
lock (ActivityOperationLock)
|
|
|
|
{
|
|
|
|
KernelContext.CriticalSection.Enter();
|
|
|
|
|
|
|
|
if ((_forcePauseFlags & ThreadSchedState.ThreadPauseFlag) == 0)
|
|
|
|
{
|
|
|
|
KernelContext.CriticalSection.Leave();
|
|
|
|
|
|
|
|
return KernelResult.InvalidState;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!TerminationRequested)
|
|
|
|
{
|
|
|
|
context = GetCurrentContext();
|
|
|
|
}
|
|
|
|
|
|
|
|
KernelContext.CriticalSection.Leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
return KernelResult.Success;
|
|
|
|
}
|
|
|
|
|
|
|
|
private static uint GetPsr(ARMeilleure.State.ExecutionContext context)
|
|
|
|
{
|
|
|
|
return (context.GetPstateFlag(ARMeilleure.State.PState.NFlag) ? (1U << (int)ARMeilleure.State.PState.NFlag) : 0U) |
|
|
|
|
(context.GetPstateFlag(ARMeilleure.State.PState.ZFlag) ? (1U << (int)ARMeilleure.State.PState.ZFlag) : 0U) |
|
|
|
|
(context.GetPstateFlag(ARMeilleure.State.PState.CFlag) ? (1U << (int)ARMeilleure.State.PState.CFlag) : 0U) |
|
|
|
|
(context.GetPstateFlag(ARMeilleure.State.PState.VFlag) ? (1U << (int)ARMeilleure.State.PState.VFlag) : 0U);
|
|
|
|
}
|
|
|
|
|
|
|
|
private ThreadContext GetCurrentContext()
|
|
|
|
{
|
|
|
|
const int MaxRegistersAArch32 = 15;
|
|
|
|
const int MaxFpuRegistersAArch32 = 16;
|
|
|
|
|
|
|
|
ThreadContext context = new ThreadContext();
|
|
|
|
|
|
|
|
if (Owner.Flags.HasFlag(ProcessCreationFlags.Is64Bit))
|
|
|
|
{
|
|
|
|
for (int i = 0; i < context.Registers.Length; i++)
|
|
|
|
{
|
|
|
|
context.Registers[i] = Context.GetX(i);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (int i = 0; i < context.FpuRegisters.Length; i++)
|
|
|
|
{
|
|
|
|
context.FpuRegisters[i] = Context.GetV(i);
|
|
|
|
}
|
|
|
|
|
|
|
|
context.Fp = Context.GetX(29);
|
|
|
|
context.Lr = Context.GetX(30);
|
|
|
|
context.Sp = Context.GetX(31);
|
|
|
|
context.Pc = (ulong)LastPc;
|
|
|
|
context.Pstate = GetPsr(Context);
|
|
|
|
context.Tpidr = (ulong)Context.Tpidr;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
for (int i = 0; i < MaxRegistersAArch32; i++)
|
|
|
|
{
|
|
|
|
context.Registers[i] = (uint)Context.GetX(i);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (int i = 0; i < MaxFpuRegistersAArch32; i++)
|
|
|
|
{
|
|
|
|
context.FpuRegisters[i] = Context.GetV(i);
|
|
|
|
}
|
|
|
|
|
|
|
|
context.Pc = (uint)LastPc;
|
|
|
|
context.Pstate = GetPsr(Context);
|
|
|
|
context.Tpidr = (uint)Context.Tpidr;
|
|
|
|
}
|
|
|
|
|
|
|
|
context.Fpcr = (uint)Context.Fpcr;
|
|
|
|
context.Fpsr = (uint)Context.Fpsr;
|
|
|
|
|
|
|
|
return context;
|
|
|
|
}
|
|
|
|
|
2018-09-19 00:36:43 +01:00
|
|
|
public void CancelSynchronization()
|
|
|
|
{
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2018-11-28 22:18:09 +00:00
|
|
|
if ((SchedFlags & ThreadSchedState.LowMask) != ThreadSchedState.Paused || !WaitingSync)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
|
|
|
SyncCancelled = true;
|
|
|
|
}
|
2018-11-28 22:18:09 +00:00
|
|
|
else if (Withholder != null)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2018-11-28 22:18:09 +00:00
|
|
|
Withholder.Remove(WithholderNode);
|
2018-09-19 00:36:43 +01:00
|
|
|
|
|
|
|
SetNewSchedFlags(ThreadSchedState.Running);
|
2018-04-21 20:07:16 +01:00
|
|
|
|
2018-11-28 22:18:09 +00:00
|
|
|
Withholder = null;
|
2018-06-22 03:05:42 +01:00
|
|
|
|
2018-09-19 00:36:43 +01:00
|
|
|
SyncCancelled = true;
|
2018-06-22 03:05:42 +01:00
|
|
|
}
|
2018-09-19 00:36:43 +01:00
|
|
|
else
|
|
|
|
{
|
2020-12-01 23:23:43 +00:00
|
|
|
SignaledObj = null;
|
2018-12-18 05:33:36 +00:00
|
|
|
ObjSyncResult = KernelResult.Cancelled;
|
2018-09-19 00:36:43 +01:00
|
|
|
|
|
|
|
SetNewSchedFlags(ThreadSchedState.Running);
|
|
|
|
|
|
|
|
SyncCancelled = false;
|
|
|
|
}
|
|
|
|
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
|
2022-01-29 21:18:03 +00:00
|
|
|
public KernelResult SetCoreAndAffinityMask(int newCore, ulong newAffinityMask)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2021-12-30 09:55:06 +00:00
|
|
|
lock (ActivityOperationLock)
|
|
|
|
{
|
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2021-12-30 09:55:06 +00:00
|
|
|
bool isCoreMigrationDisabled = _coreMigrationDisableCount != 0;
|
2018-05-13 04:22:42 +01:00
|
|
|
|
2021-12-30 09:55:06 +00:00
|
|
|
// The value -3 is "do not change the preferred core".
|
|
|
|
if (newCore == -3)
|
|
|
|
{
|
|
|
|
newCore = isCoreMigrationDisabled ? _originalPreferredCore : PreferredCore;
|
|
|
|
|
2022-01-29 21:18:03 +00:00
|
|
|
if ((newAffinityMask & (1UL << newCore)) == 0)
|
2021-12-30 09:55:06 +00:00
|
|
|
{
|
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-05-13 04:22:42 +01:00
|
|
|
|
2021-12-30 09:55:06 +00:00
|
|
|
return KernelResult.InvalidCombination;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (isCoreMigrationDisabled)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2021-12-30 09:55:06 +00:00
|
|
|
_originalPreferredCore = newCore;
|
|
|
|
_originalAffinityMask = newAffinityMask;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2022-01-29 21:18:03 +00:00
|
|
|
ulong oldAffinityMask = AffinityMask;
|
2021-12-30 09:55:06 +00:00
|
|
|
|
|
|
|
PreferredCore = newCore;
|
|
|
|
AffinityMask = newAffinityMask;
|
|
|
|
|
|
|
|
if (oldAffinityMask != newAffinityMask)
|
|
|
|
{
|
|
|
|
int oldCore = ActiveCore;
|
|
|
|
|
|
|
|
if (oldCore >= 0 && ((AffinityMask >> oldCore) & 1) == 0)
|
|
|
|
{
|
|
|
|
if (PreferredCore < 0)
|
|
|
|
{
|
2022-01-29 21:18:03 +00:00
|
|
|
ActiveCore = sizeof(ulong) * 8 - 1 - BitOperations.LeadingZeroCount(AffinityMask);
|
2021-12-30 09:55:06 +00:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
ActiveCore = PreferredCore;
|
|
|
|
}
|
|
|
|
}
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2021-12-30 09:55:06 +00:00
|
|
|
AdjustSchedulingForNewAffinity(oldAffinityMask, oldCore);
|
|
|
|
}
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
|
2021-12-30 09:55:06 +00:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2021-12-30 09:55:06 +00:00
|
|
|
bool targetThreadPinned = true;
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2021-12-30 09:55:06 +00:00
|
|
|
while (targetThreadPinned)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2021-12-30 09:55:06 +00:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2021-12-30 09:55:06 +00:00
|
|
|
if (TerminationRequested)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2021-12-30 09:55:06 +00:00
|
|
|
KernelContext.CriticalSection.Leave();
|
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
targetThreadPinned = false;
|
|
|
|
|
|
|
|
int coreNumber = GetEffectiveRunningCore();
|
|
|
|
bool isPinnedThreadCurrentlyRunning = coreNumber >= 0;
|
|
|
|
|
2022-01-29 21:18:03 +00:00
|
|
|
if (isPinnedThreadCurrentlyRunning && ((1UL << coreNumber) & AffinityMask) == 0)
|
2021-12-30 09:55:06 +00:00
|
|
|
{
|
|
|
|
if (IsPinned)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2021-12-30 09:55:06 +00:00
|
|
|
KThread currentThread = KernelStatic.GetCurrentThread();
|
|
|
|
|
|
|
|
if (currentThread.TerminationRequested)
|
|
|
|
{
|
|
|
|
KernelContext.CriticalSection.Leave();
|
|
|
|
|
|
|
|
return KernelResult.ThreadTerminating;
|
|
|
|
}
|
|
|
|
|
|
|
|
_pinnedWaiters.AddLast(currentThread);
|
|
|
|
|
|
|
|
currentThread.Reschedule(ThreadSchedState.Paused);
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2021-12-30 09:55:06 +00:00
|
|
|
targetThreadPinned = true;
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-12-30 09:55:06 +00:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
|
2021-12-30 09:55:06 +00:00
|
|
|
return KernelResult.Success;
|
|
|
|
}
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
private void CombineForcePauseFlags()
|
|
|
|
{
|
2020-12-01 23:23:43 +00:00
|
|
|
ThreadSchedState oldFlags = SchedFlags;
|
2018-12-06 11:16:24 +00:00
|
|
|
ThreadSchedState lowNibble = SchedFlags & ThreadSchedState.LowMask;
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2021-12-30 09:55:06 +00:00
|
|
|
SchedFlags = lowNibble | (_forcePauseFlags & _forcePausePermissionFlags);
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
AdjustScheduling(oldFlags);
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
private void SetNewSchedFlags(ThreadSchedState newFlags)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
ThreadSchedState oldFlags = SchedFlags;
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
SchedFlags = (oldFlags & ThreadSchedState.HighMask) | newFlags;
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
if ((oldFlags & ThreadSchedState.LowMask) != newFlags)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2018-12-06 11:16:24 +00:00
|
|
|
AdjustScheduling(oldFlags);
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
public void ReleaseAndResume()
|
|
|
|
{
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2018-11-28 22:18:09 +00:00
|
|
|
if ((SchedFlags & ThreadSchedState.LowMask) == ThreadSchedState.Paused)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2018-11-28 22:18:09 +00:00
|
|
|
if (Withholder != null)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2018-11-28 22:18:09 +00:00
|
|
|
Withholder.Remove(WithholderNode);
|
2018-09-19 00:36:43 +01:00
|
|
|
|
|
|
|
SetNewSchedFlags(ThreadSchedState.Running);
|
|
|
|
|
2018-11-28 22:18:09 +00:00
|
|
|
Withholder = null;
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
SetNewSchedFlags(ThreadSchedState.Running);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
public void Reschedule(ThreadSchedState newFlags)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
ThreadSchedState oldFlags = SchedFlags;
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
SchedFlags = (oldFlags & ThreadSchedState.HighMask) |
|
|
|
|
(newFlags & ThreadSchedState.LowMask);
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
AdjustScheduling(oldFlags);
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
public void AddMutexWaiter(KThread requester)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2018-12-06 11:16:24 +00:00
|
|
|
AddToMutexWaitersList(requester);
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
requester.MutexOwner = this;
|
2018-09-19 00:36:43 +01:00
|
|
|
|
|
|
|
UpdatePriorityInheritance();
|
|
|
|
}
|
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
public void RemoveMutexWaiter(KThread thread)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2018-12-06 11:16:24 +00:00
|
|
|
if (thread._mutexWaiterNode?.List != null)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2018-12-06 11:16:24 +00:00
|
|
|
_mutexWaiters.Remove(thread._mutexWaiterNode);
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
thread.MutexOwner = null;
|
2018-09-19 00:36:43 +01:00
|
|
|
|
|
|
|
UpdatePriorityInheritance();
|
|
|
|
}
|
|
|
|
|
2018-12-18 05:33:36 +00:00
|
|
|
public KThread RelinquishMutex(ulong mutexAddress, out int count)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2018-12-06 11:16:24 +00:00
|
|
|
count = 0;
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
if (_mutexWaiters.First == null)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
|
|
|
return null;
|
|
|
|
}
|
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
KThread newMutexOwner = null;
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
LinkedListNode<KThread> currentNode = _mutexWaiters.First;
|
2018-09-19 00:36:43 +01:00
|
|
|
|
|
|
|
do
|
|
|
|
{
|
2019-07-02 03:39:22 +01:00
|
|
|
// Skip all threads that are not waiting for this mutex.
|
2018-12-06 11:16:24 +00:00
|
|
|
while (currentNode != null && currentNode.Value.MutexAddress != mutexAddress)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2018-12-06 11:16:24 +00:00
|
|
|
currentNode = currentNode.Next;
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
if (currentNode == null)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
LinkedListNode<KThread> nextNode = currentNode.Next;
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
_mutexWaiters.Remove(currentNode);
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
currentNode.Value.MutexOwner = newMutexOwner;
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
if (newMutexOwner != null)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2019-07-02 03:39:22 +01:00
|
|
|
// New owner was already selected, re-insert on new owner list.
|
2018-12-06 11:16:24 +00:00
|
|
|
newMutexOwner.AddToMutexWaitersList(currentNode.Value);
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2019-07-02 03:39:22 +01:00
|
|
|
// New owner not selected yet, use current thread.
|
2018-12-06 11:16:24 +00:00
|
|
|
newMutexOwner = currentNode.Value;
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
count++;
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
currentNode = nextNode;
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
2018-12-06 11:16:24 +00:00
|
|
|
while (currentNode != null);
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
if (newMutexOwner != null)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
|
|
|
UpdatePriorityInheritance();
|
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
newMutexOwner.UpdatePriorityInheritance();
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
return newMutexOwner;
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
private void UpdatePriorityInheritance()
|
|
|
|
{
|
2019-07-02 03:39:22 +01:00
|
|
|
// If any of the threads waiting for the mutex has
|
|
|
|
// higher priority than the current thread, then
|
|
|
|
// the current thread inherits that priority.
|
2018-12-06 11:16:24 +00:00
|
|
|
int highestPriority = BasePriority;
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
if (_mutexWaiters.First != null)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2018-12-06 11:16:24 +00:00
|
|
|
int waitingDynamicPriority = _mutexWaiters.First.Value.DynamicPriority;
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
if (waitingDynamicPriority < highestPriority)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2018-12-06 11:16:24 +00:00
|
|
|
highestPriority = waitingDynamicPriority;
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
if (highestPriority != DynamicPriority)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2018-12-06 11:16:24 +00:00
|
|
|
int oldPriority = DynamicPriority;
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
DynamicPriority = highestPriority;
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
AdjustSchedulingForNewPriority(oldPriority);
|
2018-09-19 00:36:43 +01:00
|
|
|
|
|
|
|
if (MutexOwner != null)
|
|
|
|
{
|
2019-07-02 03:39:22 +01:00
|
|
|
// Remove and re-insert to ensure proper sorting based on new priority.
|
2018-12-06 11:16:24 +00:00
|
|
|
MutexOwner._mutexWaiters.Remove(_mutexWaiterNode);
|
2018-09-19 00:36:43 +01:00
|
|
|
|
|
|
|
MutexOwner.AddToMutexWaitersList(this);
|
|
|
|
|
|
|
|
MutexOwner.UpdatePriorityInheritance();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
private void AddToMutexWaitersList(KThread thread)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2018-12-06 11:16:24 +00:00
|
|
|
LinkedListNode<KThread> nextPrio = _mutexWaiters.First;
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
int currentPriority = thread.DynamicPriority;
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
while (nextPrio != null && nextPrio.Value.DynamicPriority <= currentPriority)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2018-12-06 11:16:24 +00:00
|
|
|
nextPrio = nextPrio.Next;
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
if (nextPrio != null)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2018-12-06 11:16:24 +00:00
|
|
|
thread._mutexWaiterNode = _mutexWaiters.AddBefore(nextPrio, thread);
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2018-12-06 11:16:24 +00:00
|
|
|
thread._mutexWaiterNode = _mutexWaiters.AddLast(thread);
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
private void AdjustScheduling(ThreadSchedState oldFlags)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2018-12-06 11:16:24 +00:00
|
|
|
if (oldFlags == SchedFlags)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
if (!IsSchedulable)
|
|
|
|
{
|
2021-09-11 21:08:25 +01:00
|
|
|
if (!_forcedUnschedulable)
|
2020-12-09 22:20:05 +00:00
|
|
|
{
|
2021-09-11 21:08:25 +01:00
|
|
|
// Ensure our thread is running and we have an event.
|
|
|
|
StartHostThread();
|
|
|
|
|
|
|
|
// If the thread is not schedulable, we want to just run or pause
|
|
|
|
// it directly as we don't care about priority or the core it is
|
|
|
|
// running on in this case.
|
|
|
|
if (SchedFlags == ThreadSchedState.Running)
|
|
|
|
{
|
|
|
|
_schedulerWaitEvent.Set();
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
_schedulerWaitEvent.Reset();
|
|
|
|
}
|
2020-12-09 22:20:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
if (oldFlags == ThreadSchedState.Running)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2019-07-02 03:39:22 +01:00
|
|
|
// Was running, now it's stopped.
|
2020-12-09 22:20:05 +00:00
|
|
|
if (ActiveCore >= 0)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
KernelContext.PriorityQueue.Unschedule(DynamicPriority, ActiveCore, this);
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
for (int core = 0; core < KScheduler.CpuCoresCount; core++)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
if (core != ActiveCore && ((AffinityMask >> core) & 1) != 0)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
KernelContext.PriorityQueue.Unsuggest(DynamicPriority, core, this);
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else if (SchedFlags == ThreadSchedState.Running)
|
|
|
|
{
|
2019-07-02 03:39:22 +01:00
|
|
|
// Was stopped, now it's running.
|
2020-12-09 22:20:05 +00:00
|
|
|
if (ActiveCore >= 0)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
KernelContext.PriorityQueue.Schedule(DynamicPriority, ActiveCore, this);
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
for (int core = 0; core < KScheduler.CpuCoresCount; core++)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
if (core != ActiveCore && ((AffinityMask >> core) & 1) != 0)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
KernelContext.PriorityQueue.Suggest(DynamicPriority, core, this);
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
KernelContext.ThreadReselectionRequested = true;
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
private void AdjustSchedulingForNewPriority(int oldPriority)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
if (SchedFlags != ThreadSchedState.Running || !IsSchedulable)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2019-07-02 03:39:22 +01:00
|
|
|
// Remove thread from the old priority queues.
|
2020-12-09 22:20:05 +00:00
|
|
|
if (ActiveCore >= 0)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
KernelContext.PriorityQueue.Unschedule(oldPriority, ActiveCore, this);
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
for (int core = 0; core < KScheduler.CpuCoresCount; core++)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
if (core != ActiveCore && ((AffinityMask >> core) & 1) != 0)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
KernelContext.PriorityQueue.Unsuggest(oldPriority, core, this);
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-07-02 03:39:22 +01:00
|
|
|
// Add thread to the new priority queues.
|
2020-12-09 22:20:05 +00:00
|
|
|
KThread currentThread = KernelStatic.GetCurrentThread();
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
if (ActiveCore >= 0)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2018-12-06 11:16:24 +00:00
|
|
|
if (currentThread == this)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
KernelContext.PriorityQueue.SchedulePrepend(DynamicPriority, ActiveCore, this);
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
KernelContext.PriorityQueue.Schedule(DynamicPriority, ActiveCore, this);
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
for (int core = 0; core < KScheduler.CpuCoresCount; core++)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
if (core != ActiveCore && ((AffinityMask >> core) & 1) != 0)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
KernelContext.PriorityQueue.Suggest(DynamicPriority, core, this);
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
KernelContext.ThreadReselectionRequested = true;
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
|
2022-01-29 21:18:03 +00:00
|
|
|
private void AdjustSchedulingForNewAffinity(ulong oldAffinityMask, int oldCore)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
if (SchedFlags != ThreadSchedState.Running || DynamicPriority >= KScheduler.PrioritiesCount || !IsSchedulable)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2019-07-02 03:39:22 +01:00
|
|
|
// Remove thread from the old priority queues.
|
2018-12-06 11:16:24 +00:00
|
|
|
for (int core = 0; core < KScheduler.CpuCoresCount; core++)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2018-12-06 11:16:24 +00:00
|
|
|
if (((oldAffinityMask >> core) & 1) != 0)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2018-12-06 11:16:24 +00:00
|
|
|
if (core == oldCore)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
KernelContext.PriorityQueue.Unschedule(DynamicPriority, core, this);
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
KernelContext.PriorityQueue.Unsuggest(DynamicPriority, core, this);
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-07-02 03:39:22 +01:00
|
|
|
// Add thread to the new priority queues.
|
2018-12-06 11:16:24 +00:00
|
|
|
for (int core = 0; core < KScheduler.CpuCoresCount; core++)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2018-12-06 11:16:24 +00:00
|
|
|
if (((AffinityMask >> core) & 1) != 0)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
if (core == ActiveCore)
|
2018-09-19 00:36:43 +01:00
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
KernelContext.PriorityQueue.Schedule(DynamicPriority, core, this);
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
KernelContext.PriorityQueue.Suggest(DynamicPriority, core, this);
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
KernelContext.ThreadReselectionRequested = true;
|
2018-09-19 00:36:43 +01:00
|
|
|
}
|
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
public void SetEntryArguments(long argsPtr, int threadHandle)
|
2018-11-28 22:18:09 +00:00
|
|
|
{
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 19:56:22 +01:00
|
|
|
Context.SetX(0, (ulong)argsPtr);
|
|
|
|
Context.SetX(1, (ulong)threadHandle);
|
2018-11-28 22:18:09 +00:00
|
|
|
}
|
|
|
|
|
2018-09-19 00:36:43 +01:00
|
|
|
public void TimeUp()
|
|
|
|
{
|
2018-11-28 22:18:09 +00:00
|
|
|
ReleaseAndResume();
|
|
|
|
}
|
|
|
|
|
2019-03-15 03:37:54 +00:00
|
|
|
public string GetGuestStackTrace()
|
|
|
|
{
|
2021-05-21 00:27:16 +01:00
|
|
|
return Owner.Debugger.GetGuestStackTrace(this);
|
|
|
|
}
|
|
|
|
|
|
|
|
public string GetGuestRegisterPrintout()
|
|
|
|
{
|
|
|
|
return Owner.Debugger.GetCpuRegisterPrintout(this);
|
2019-03-15 03:37:54 +00:00
|
|
|
}
|
|
|
|
|
2018-11-28 22:18:09 +00:00
|
|
|
public void PrintGuestStackTrace()
|
|
|
|
{
|
2020-08-04 00:32:53 +01:00
|
|
|
Logger.Info?.Print(LogClass.Cpu, $"Guest stack trace:\n{GetGuestStackTrace()}\n");
|
2018-11-28 22:18:09 +00:00
|
|
|
}
|
|
|
|
|
2021-05-21 00:27:16 +01:00
|
|
|
public void PrintGuestRegisterPrintout()
|
|
|
|
{
|
|
|
|
Logger.Info?.Print(LogClass.Cpu, $"Guest CPU registers:\n{GetGuestRegisterPrintout()}\n");
|
|
|
|
}
|
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
public void AddCpuTime(long ticks)
|
|
|
|
{
|
|
|
|
Interlocked.Add(ref _totalTimeRunning, ticks);
|
|
|
|
}
|
|
|
|
|
|
|
|
public void StartHostThread()
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 19:56:22 +01:00
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
if (_schedulerWaitEvent == null)
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 19:56:22 +01:00
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
var schedulerWaitEvent = new ManualResetEvent(false);
|
|
|
|
|
|
|
|
if (Interlocked.Exchange(ref _schedulerWaitEvent, schedulerWaitEvent) == null)
|
|
|
|
{
|
|
|
|
HostThread.Start();
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
schedulerWaitEvent.Dispose();
|
|
|
|
}
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 19:56:22 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-12-01 23:23:43 +00:00
|
|
|
private void ThreadStart()
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 19:56:22 +01:00
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
_schedulerWaitEvent.WaitOne();
|
|
|
|
KernelStatic.SetKernelContext(KernelContext, this);
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 19:56:22 +01:00
|
|
|
|
2020-12-01 23:23:43 +00:00
|
|
|
if (_customThreadStart != null)
|
|
|
|
{
|
|
|
|
_customThreadStart();
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
Owner.Context.Execute(Context, _entrypoint);
|
|
|
|
}
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 19:56:22 +01:00
|
|
|
|
2020-12-01 23:23:43 +00:00
|
|
|
Context.Dispose();
|
2020-12-09 22:20:05 +00:00
|
|
|
_schedulerWaitEvent.Dispose();
|
2019-01-18 22:26:39 +00:00
|
|
|
}
|
2018-11-28 22:18:09 +00:00
|
|
|
|
2020-12-09 22:20:05 +00:00
|
|
|
public void MakeUnschedulable()
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 19:56:22 +01:00
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
_forcedUnschedulable = true;
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 19:56:22 +01:00
|
|
|
}
|
|
|
|
|
2019-01-18 22:26:39 +00:00
|
|
|
public override bool IsSignaled()
|
|
|
|
{
|
2020-12-09 22:20:05 +00:00
|
|
|
return _hasExited != 0;
|
2019-01-18 22:26:39 +00:00
|
|
|
}
|
2018-11-28 22:18:09 +00:00
|
|
|
|
2019-01-18 22:26:39 +00:00
|
|
|
protected override void Destroy()
|
|
|
|
{
|
|
|
|
if (_hasBeenInitialized)
|
|
|
|
{
|
|
|
|
FreeResources();
|
|
|
|
|
|
|
|
bool released = Owner != null || _hasBeenReleased;
|
|
|
|
|
|
|
|
if (Owner != null)
|
|
|
|
{
|
|
|
|
Owner.ResourceLimit?.Release(LimitableResource.Thread, 1, released ? 0 : 1);
|
|
|
|
|
|
|
|
Owner.DecrementReferenceCount();
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.ResourceLimit.Release(LimitableResource.Thread, 1, released ? 0 : 1);
|
2019-01-18 22:26:39 +00:00
|
|
|
}
|
|
|
|
}
|
2018-11-28 22:18:09 +00:00
|
|
|
}
|
|
|
|
|
2019-01-18 22:26:39 +00:00
|
|
|
private void FreeResources()
|
2018-11-28 22:18:09 +00:00
|
|
|
{
|
|
|
|
Owner?.RemoveThread(this);
|
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
if (_tlsAddress != 0 && Owner.FreeThreadLocalStorage(_tlsAddress) != KernelResult.Success)
|
2018-11-28 22:18:09 +00:00
|
|
|
{
|
|
|
|
throw new InvalidOperationException("Unexpected failure freeing thread local storage.");
|
|
|
|
}
|
|
|
|
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-11-28 22:18:09 +00:00
|
|
|
|
2019-07-02 03:39:22 +01:00
|
|
|
// Wake up all threads that may be waiting for a mutex being held by this thread.
|
2018-12-06 11:16:24 +00:00
|
|
|
foreach (KThread thread in _mutexWaiters)
|
2018-11-28 22:18:09 +00:00
|
|
|
{
|
2020-12-01 23:23:43 +00:00
|
|
|
thread.MutexOwner = null;
|
2021-12-30 09:55:06 +00:00
|
|
|
thread._originalPreferredCore = 0;
|
2020-12-01 23:23:43 +00:00
|
|
|
thread.ObjSyncResult = KernelResult.InvalidState;
|
2018-11-28 22:18:09 +00:00
|
|
|
|
2018-12-06 11:16:24 +00:00
|
|
|
thread.ReleaseAndResume();
|
2018-11-28 22:18:09 +00:00
|
|
|
}
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2020-05-04 04:41:29 +01:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-19 00:36:43 +01:00
|
|
|
|
2018-11-28 22:18:09 +00:00
|
|
|
Owner?.DecrementThreadCountAndTerminateIfZero();
|
2018-02-04 23:08:20 +00:00
|
|
|
}
|
2021-12-30 09:55:06 +00:00
|
|
|
|
|
|
|
public void Pin()
|
|
|
|
{
|
|
|
|
IsPinned = true;
|
|
|
|
_coreMigrationDisableCount++;
|
|
|
|
|
|
|
|
int activeCore = ActiveCore;
|
|
|
|
|
|
|
|
_originalPreferredCore = PreferredCore;
|
|
|
|
_originalAffinityMask = AffinityMask;
|
|
|
|
|
|
|
|
ActiveCore = CurrentCore;
|
|
|
|
PreferredCore = CurrentCore;
|
2022-01-29 21:18:03 +00:00
|
|
|
AffinityMask = 1UL << CurrentCore;
|
2021-12-30 09:55:06 +00:00
|
|
|
|
|
|
|
if (activeCore != CurrentCore || _originalAffinityMask != AffinityMask)
|
|
|
|
{
|
|
|
|
AdjustSchedulingForNewAffinity(_originalAffinityMask, activeCore);
|
|
|
|
}
|
|
|
|
|
|
|
|
_originalBasePriority = BasePriority;
|
|
|
|
BasePriority = Math.Min(_originalBasePriority, BitOperations.TrailingZeroCount(Owner.Capabilities.AllowedThreadPriosMask) - 1);
|
|
|
|
UpdatePriorityInheritance();
|
|
|
|
|
|
|
|
// Disallows thread pausing
|
|
|
|
_forcePausePermissionFlags &= ~ThreadSchedState.ThreadPauseFlag;
|
|
|
|
CombineForcePauseFlags();
|
|
|
|
|
|
|
|
// TODO: Assign reduced SVC permissions
|
|
|
|
}
|
|
|
|
|
|
|
|
public void Unpin()
|
|
|
|
{
|
|
|
|
IsPinned = false;
|
|
|
|
_coreMigrationDisableCount--;
|
|
|
|
|
2022-01-29 21:18:03 +00:00
|
|
|
ulong affinityMask = AffinityMask;
|
2021-12-30 09:55:06 +00:00
|
|
|
int activeCore = ActiveCore;
|
|
|
|
|
|
|
|
PreferredCore = _originalPreferredCore;
|
|
|
|
AffinityMask = _originalAffinityMask;
|
|
|
|
|
|
|
|
if (AffinityMask != affinityMask)
|
|
|
|
{
|
2022-01-29 21:18:03 +00:00
|
|
|
if ((AffinityMask & 1UL << ActiveCore) != 0)
|
2021-12-30 09:55:06 +00:00
|
|
|
{
|
|
|
|
if (PreferredCore >= 0)
|
|
|
|
{
|
|
|
|
ActiveCore = PreferredCore;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
ActiveCore = sizeof(ulong) * 8 - 1 - BitOperations.LeadingZeroCount((ulong)AffinityMask);
|
|
|
|
}
|
|
|
|
|
|
|
|
AdjustSchedulingForNewAffinity(affinityMask, activeCore);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
BasePriority = _originalBasePriority;
|
|
|
|
UpdatePriorityInheritance();
|
|
|
|
|
|
|
|
if (!TerminationRequested)
|
|
|
|
{
|
|
|
|
// Allows thread pausing
|
|
|
|
_forcePausePermissionFlags |= ThreadSchedState.ThreadPauseFlag;
|
|
|
|
CombineForcePauseFlags();
|
|
|
|
|
|
|
|
// TODO: Restore SVC permissions
|
|
|
|
}
|
|
|
|
|
|
|
|
// Wake up waiters
|
|
|
|
foreach (KThread waiter in _pinnedWaiters)
|
|
|
|
{
|
|
|
|
waiter.ReleaseAndResume();
|
|
|
|
}
|
|
|
|
|
|
|
|
_pinnedWaiters.Clear();
|
|
|
|
}
|
|
|
|
|
|
|
|
public void SynchronizePreemptionState()
|
|
|
|
{
|
|
|
|
KernelContext.CriticalSection.Enter();
|
|
|
|
|
|
|
|
if (Owner != null && Owner.PinnedThreads[CurrentCore] == this)
|
|
|
|
{
|
|
|
|
ClearUserInterruptFlag();
|
|
|
|
|
|
|
|
Owner.UnpinThread(this);
|
|
|
|
}
|
|
|
|
|
|
|
|
KernelContext.CriticalSection.Leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
public ushort GetUserDisableCount()
|
|
|
|
{
|
|
|
|
return Owner.CpuMemory.Read<ushort>(_tlsAddress + TlsUserDisableCountOffset);
|
|
|
|
}
|
|
|
|
|
|
|
|
public void SetUserInterruptFlag()
|
|
|
|
{
|
|
|
|
Owner.CpuMemory.Write<ushort>(_tlsAddress + TlsUserInterruptFlagOffset, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
public void ClearUserInterruptFlag()
|
|
|
|
{
|
|
|
|
Owner.CpuMemory.Write<ushort>(_tlsAddress + TlsUserInterruptFlagOffset, 0);
|
|
|
|
}
|
2018-02-04 23:08:20 +00:00
|
|
|
}
|
|
|
|
}
|