Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 19:56:22 +01:00
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using ARMeilleure.State;
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2018-12-18 05:33:36 +00:00
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using Ryujinx.Common.Logging;
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using Ryujinx.HLE.HOS.Kernel.Common;
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using System;
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using System.Collections.Generic;
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using System.Reflection;
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using System.Reflection.Emit;
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namespace Ryujinx.HLE.HOS.Kernel.SupervisorCall
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{
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2020-05-04 04:41:29 +01:00
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static class SyscallTable
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2018-12-18 05:33:36 +00:00
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{
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2020-01-13 02:04:28 +00:00
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private const int SvcFuncMaxArguments64 = 8;
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private const int SvcFuncMaxArguments32 = 4;
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private const int SvcMax = 0x80;
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2018-12-18 05:33:36 +00:00
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2020-05-04 04:41:29 +01:00
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public static Action<Syscall32, ExecutionContext>[] SvcTable32 { get; }
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public static Action<Syscall64, ExecutionContext>[] SvcTable64 { get; }
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2018-12-18 05:33:36 +00:00
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2020-05-04 04:41:29 +01:00
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static SyscallTable()
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2018-12-18 05:33:36 +00:00
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{
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2020-05-04 04:41:29 +01:00
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SvcTable32 = new Action<Syscall32, ExecutionContext>[SvcMax];
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SvcTable64 = new Action<Syscall64, ExecutionContext>[SvcMax];
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2020-01-13 02:04:28 +00:00
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Dictionary<int, string> svcFuncs64 = new Dictionary<int, string>
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2018-12-18 05:33:36 +00:00
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{
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2020-07-17 05:19:07 +01:00
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{ 0x01, nameof(Syscall64.SetHeapSize64) },
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2021-10-24 00:24:49 +01:00
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{ 0x02, nameof(Syscall64.SetMemoryPermission64) },
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2020-07-17 05:19:07 +01:00
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{ 0x03, nameof(Syscall64.SetMemoryAttribute64) },
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{ 0x04, nameof(Syscall64.MapMemory64) },
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{ 0x05, nameof(Syscall64.UnmapMemory64) },
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{ 0x06, nameof(Syscall64.QueryMemory64) },
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{ 0x07, nameof(Syscall64.ExitProcess64) },
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{ 0x08, nameof(Syscall64.CreateThread64) },
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{ 0x09, nameof(Syscall64.StartThread64) },
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{ 0x0a, nameof(Syscall64.ExitThread64) },
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{ 0x0b, nameof(Syscall64.SleepThread64) },
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{ 0x0c, nameof(Syscall64.GetThreadPriority64) },
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{ 0x0d, nameof(Syscall64.SetThreadPriority64) },
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{ 0x0e, nameof(Syscall64.GetThreadCoreMask64) },
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{ 0x0f, nameof(Syscall64.SetThreadCoreMask64) },
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{ 0x10, nameof(Syscall64.GetCurrentProcessorNumber64) },
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{ 0x11, nameof(Syscall64.SignalEvent64) },
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{ 0x12, nameof(Syscall64.ClearEvent64) },
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{ 0x13, nameof(Syscall64.MapSharedMemory64) },
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{ 0x14, nameof(Syscall64.UnmapSharedMemory64) },
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{ 0x15, nameof(Syscall64.CreateTransferMemory64) },
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{ 0x16, nameof(Syscall64.CloseHandle64) },
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{ 0x17, nameof(Syscall64.ResetSignal64) },
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{ 0x18, nameof(Syscall64.WaitSynchronization64) },
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{ 0x19, nameof(Syscall64.CancelSynchronization64) },
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{ 0x1a, nameof(Syscall64.ArbitrateLock64) },
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{ 0x1b, nameof(Syscall64.ArbitrateUnlock64) },
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{ 0x1c, nameof(Syscall64.WaitProcessWideKeyAtomic64) },
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{ 0x1d, nameof(Syscall64.SignalProcessWideKey64) },
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{ 0x1e, nameof(Syscall64.GetSystemTick64) },
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{ 0x1f, nameof(Syscall64.ConnectToNamedPort64) },
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{ 0x21, nameof(Syscall64.SendSyncRequest64) },
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{ 0x22, nameof(Syscall64.SendSyncRequestWithUserBuffer64) },
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{ 0x23, nameof(Syscall64.SendAsyncRequestWithUserBuffer64) },
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{ 0x24, nameof(Syscall64.GetProcessId64) },
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{ 0x25, nameof(Syscall64.GetThreadId64) },
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{ 0x26, nameof(Syscall64.Break64) },
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{ 0x27, nameof(Syscall64.OutputDebugString64) },
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{ 0x29, nameof(Syscall64.GetInfo64) },
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{ 0x2c, nameof(Syscall64.MapPhysicalMemory64) },
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{ 0x2d, nameof(Syscall64.UnmapPhysicalMemory64) },
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2021-10-24 00:40:13 +01:00
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{ 0x30, nameof(Syscall64.GetResourceLimitLimitValue64) },
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{ 0x31, nameof(Syscall64.GetResourceLimitCurrentValue64) },
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2020-07-17 05:19:07 +01:00
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{ 0x32, nameof(Syscall64.SetThreadActivity64) },
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{ 0x33, nameof(Syscall64.GetThreadContext364) },
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{ 0x34, nameof(Syscall64.WaitForAddress64) },
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{ 0x35, nameof(Syscall64.SignalToAddress64) },
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2021-12-30 09:55:06 +00:00
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{ 0x36, nameof(Syscall64.SynchronizePreemptionState64) },
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2021-10-24 00:40:13 +01:00
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{ 0x37, nameof(Syscall64.GetResourceLimitPeakValue64) },
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2020-07-17 05:19:07 +01:00
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{ 0x40, nameof(Syscall64.CreateSession64) },
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{ 0x41, nameof(Syscall64.AcceptSession64) },
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{ 0x43, nameof(Syscall64.ReplyAndReceive64) },
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{ 0x44, nameof(Syscall64.ReplyAndReceiveWithUserBuffer64) },
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{ 0x45, nameof(Syscall64.CreateEvent64) },
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2022-05-03 12:16:31 +01:00
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{ 0x4b, nameof(Syscall64.CreateCodeMemory64) },
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{ 0x4c, nameof(Syscall64.ControlCodeMemory64) },
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2021-06-23 20:52:11 +01:00
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{ 0x51, nameof(Syscall64.MapTransferMemory64) },
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{ 0x52, nameof(Syscall64.UnmapTransferMemory64) },
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2020-07-17 05:19:07 +01:00
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{ 0x65, nameof(Syscall64.GetProcessList64) },
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{ 0x6f, nameof(Syscall64.GetSystemInfo64) },
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{ 0x70, nameof(Syscall64.CreatePort64) },
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{ 0x71, nameof(Syscall64.ManageNamedPort64) },
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{ 0x72, nameof(Syscall64.ConnectToPort64) },
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{ 0x73, nameof(Syscall64.SetProcessMemoryPermission64) },
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2022-05-03 12:16:31 +01:00
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{ 0x74, nameof(Syscall64.MapProcessMemory64) },
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{ 0x75, nameof(Syscall64.UnmapProcessMemory64) },
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2020-07-17 05:19:07 +01:00
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{ 0x77, nameof(Syscall64.MapProcessCodeMemory64) },
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{ 0x78, nameof(Syscall64.UnmapProcessCodeMemory64) },
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2021-10-24 00:40:13 +01:00
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{ 0x7B, nameof(Syscall64.TerminateProcess64) },
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{ 0x7D, nameof(Syscall64.CreateResourceLimit64) },
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{ 0x7E, nameof(Syscall64.SetResourceLimitLimitValue64) }
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2018-12-18 05:33:36 +00:00
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};
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2020-01-13 02:04:28 +00:00
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foreach (KeyValuePair<int, string> value in svcFuncs64)
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2018-12-18 05:33:36 +00:00
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{
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2020-05-04 04:41:29 +01:00
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SvcTable64[value.Key] = GenerateMethod<Syscall64>(value.Value, SvcFuncMaxArguments64);
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2018-12-18 05:33:36 +00:00
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}
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2020-01-13 02:04:28 +00:00
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Dictionary<int, string> svcFuncs32 = new Dictionary<int, string>
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2018-12-18 05:33:36 +00:00
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{
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2020-05-04 04:41:29 +01:00
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{ 0x01, nameof(Syscall32.SetHeapSize32) },
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2021-10-24 00:24:49 +01:00
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{ 0x02, nameof(Syscall32.SetMemoryPermission32) },
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2020-05-04 04:41:29 +01:00
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{ 0x03, nameof(Syscall32.SetMemoryAttribute32) },
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{ 0x04, nameof(Syscall32.MapMemory32) },
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{ 0x05, nameof(Syscall32.UnmapMemory32) },
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{ 0x06, nameof(Syscall32.QueryMemory32) },
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{ 0x07, nameof(Syscall32.ExitProcess32) },
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{ 0x08, nameof(Syscall32.CreateThread32) },
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{ 0x09, nameof(Syscall32.StartThread32) },
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{ 0x0a, nameof(Syscall32.ExitThread32) },
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{ 0x0b, nameof(Syscall32.SleepThread32) },
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{ 0x0c, nameof(Syscall32.GetThreadPriority32) },
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{ 0x0d, nameof(Syscall32.SetThreadPriority32) },
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{ 0x0e, nameof(Syscall32.GetThreadCoreMask32) },
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{ 0x0f, nameof(Syscall32.SetThreadCoreMask32) },
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{ 0x10, nameof(Syscall32.GetCurrentProcessorNumber32) },
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{ 0x11, nameof(Syscall32.SignalEvent32) },
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{ 0x12, nameof(Syscall32.ClearEvent32) },
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{ 0x13, nameof(Syscall32.MapSharedMemory32) },
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{ 0x14, nameof(Syscall32.UnmapSharedMemory32) },
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{ 0x15, nameof(Syscall32.CreateTransferMemory32) },
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{ 0x16, nameof(Syscall32.CloseHandle32) },
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{ 0x17, nameof(Syscall32.ResetSignal32) },
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{ 0x18, nameof(Syscall32.WaitSynchronization32) },
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{ 0x19, nameof(Syscall32.CancelSynchronization32) },
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{ 0x1a, nameof(Syscall32.ArbitrateLock32) },
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{ 0x1b, nameof(Syscall32.ArbitrateUnlock32) },
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{ 0x1c, nameof(Syscall32.WaitProcessWideKeyAtomic32) },
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{ 0x1d, nameof(Syscall32.SignalProcessWideKey32) },
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{ 0x1e, nameof(Syscall32.GetSystemTick32) },
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{ 0x1f, nameof(Syscall32.ConnectToNamedPort32) },
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{ 0x21, nameof(Syscall32.SendSyncRequest32) },
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{ 0x22, nameof(Syscall32.SendSyncRequestWithUserBuffer32) },
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{ 0x24, nameof(Syscall32.GetProcessId32) },
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{ 0x25, nameof(Syscall32.GetThreadId32) },
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{ 0x26, nameof(Syscall32.Break32) },
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{ 0x27, nameof(Syscall32.OutputDebugString32) },
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{ 0x29, nameof(Syscall32.GetInfo32) },
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{ 0x2c, nameof(Syscall32.MapPhysicalMemory32) },
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{ 0x2d, nameof(Syscall32.UnmapPhysicalMemory32) },
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2021-10-24 00:40:13 +01:00
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{ 0x30, nameof(Syscall32.GetResourceLimitLimitValue32) },
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{ 0x31, nameof(Syscall32.GetResourceLimitCurrentValue32) },
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2020-05-04 04:41:29 +01:00
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{ 0x32, nameof(Syscall32.SetThreadActivity32) },
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{ 0x33, nameof(Syscall32.GetThreadContext332) },
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{ 0x34, nameof(Syscall32.WaitForAddress32) },
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{ 0x35, nameof(Syscall32.SignalToAddress32) },
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2021-12-30 09:55:06 +00:00
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{ 0x36, nameof(Syscall32.SynchronizePreemptionState32) },
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2021-10-24 00:40:13 +01:00
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{ 0x37, nameof(Syscall32.GetResourceLimitPeakValue32) },
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2020-05-04 04:41:29 +01:00
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{ 0x40, nameof(Syscall32.CreateSession32) },
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{ 0x41, nameof(Syscall32.AcceptSession32) },
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{ 0x43, nameof(Syscall32.ReplyAndReceive32) },
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{ 0x45, nameof(Syscall32.CreateEvent32) },
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2022-05-03 12:16:31 +01:00
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{ 0x4b, nameof(Syscall32.CreateCodeMemory32) },
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{ 0x4c, nameof(Syscall32.ControlCodeMemory32) },
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2021-06-23 20:52:11 +01:00
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{ 0x51, nameof(Syscall32.MapTransferMemory32) },
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{ 0x52, nameof(Syscall32.UnmapTransferMemory32) },
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2020-05-04 04:41:29 +01:00
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{ 0x5F, nameof(Syscall32.FlushProcessDataCache32) },
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{ 0x65, nameof(Syscall32.GetProcessList32) },
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{ 0x6f, nameof(Syscall32.GetSystemInfo32) },
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{ 0x70, nameof(Syscall32.CreatePort32) },
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{ 0x71, nameof(Syscall32.ManageNamedPort32) },
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{ 0x72, nameof(Syscall32.ConnectToPort32) },
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{ 0x73, nameof(Syscall32.SetProcessMemoryPermission32) },
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2022-05-03 12:16:31 +01:00
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{ 0x74, nameof(Syscall32.MapProcessMemory32) },
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{ 0x75, nameof(Syscall32.UnmapProcessMemory32) },
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2020-05-04 04:41:29 +01:00
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{ 0x77, nameof(Syscall32.MapProcessCodeMemory32) },
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{ 0x78, nameof(Syscall32.UnmapProcessCodeMemory32) },
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2021-10-24 00:40:13 +01:00
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{ 0x7B, nameof(Syscall32.TerminateProcess32) },
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{ 0x7D, nameof(Syscall32.CreateResourceLimit32) },
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{ 0x7E, nameof(Syscall32.SetResourceLimitLimitValue32) }
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2020-01-13 02:04:28 +00:00
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};
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2018-12-18 05:33:36 +00:00
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2020-01-13 02:04:28 +00:00
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foreach (KeyValuePair<int, string> value in svcFuncs32)
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{
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2020-05-04 04:41:29 +01:00
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SvcTable32[value.Key] = GenerateMethod<Syscall32>(value.Value, SvcFuncMaxArguments32);
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2020-01-13 02:04:28 +00:00
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}
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2018-12-18 05:33:36 +00:00
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}
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2020-05-04 04:41:29 +01:00
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private static Action<T, ExecutionContext> GenerateMethod<T>(string svcName, int registerCleanCount)
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2018-12-18 05:33:36 +00:00
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{
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2020-05-04 04:41:29 +01:00
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Type[] argTypes = new Type[] { typeof(T), typeof(ExecutionContext) };
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2018-12-18 05:33:36 +00:00
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DynamicMethod method = new DynamicMethod(svcName, null, argTypes);
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2020-05-04 04:41:29 +01:00
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MethodInfo methodInfo = typeof(T).GetMethod(svcName);
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2018-12-18 05:33:36 +00:00
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ParameterInfo[] methodArgs = methodInfo.GetParameters();
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ILGenerator generator = method.GetILGenerator();
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void ConvertToArgType(Type sourceType)
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{
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CheckIfTypeIsSupported(sourceType, svcName);
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switch (Type.GetTypeCode(sourceType))
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{
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case TypeCode.UInt32: generator.Emit(OpCodes.Conv_U4); break;
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case TypeCode.Int32: generator.Emit(OpCodes.Conv_I4); break;
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case TypeCode.UInt16: generator.Emit(OpCodes.Conv_U2); break;
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case TypeCode.Int16: generator.Emit(OpCodes.Conv_I2); break;
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case TypeCode.Byte: generator.Emit(OpCodes.Conv_U1); break;
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case TypeCode.SByte: generator.Emit(OpCodes.Conv_I1); break;
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|
|
case TypeCode.Boolean:
|
|
|
|
generator.Emit(OpCodes.Conv_I4);
|
|
|
|
generator.Emit(OpCodes.Ldc_I4_1);
|
|
|
|
generator.Emit(OpCodes.And);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void ConvertToFieldType(Type sourceType)
|
|
|
|
{
|
|
|
|
CheckIfTypeIsSupported(sourceType, svcName);
|
|
|
|
|
|
|
|
switch (Type.GetTypeCode(sourceType))
|
|
|
|
{
|
|
|
|
case TypeCode.UInt32:
|
|
|
|
case TypeCode.Int32:
|
|
|
|
case TypeCode.UInt16:
|
|
|
|
case TypeCode.Int16:
|
|
|
|
case TypeCode.Byte:
|
|
|
|
case TypeCode.SByte:
|
|
|
|
case TypeCode.Boolean:
|
|
|
|
generator.Emit(OpCodes.Conv_U8);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-01-13 02:04:28 +00:00
|
|
|
RAttribute GetRegisterAttribute(ParameterInfo parameterInfo)
|
|
|
|
{
|
|
|
|
RAttribute argumentAttribute = (RAttribute)parameterInfo.GetCustomAttribute(typeof(RAttribute));
|
|
|
|
|
|
|
|
if (argumentAttribute == null)
|
|
|
|
{
|
|
|
|
throw new InvalidOperationException($"Method \"{svcName}\" is missing a {typeof(RAttribute).Name} attribute on parameter \"{parameterInfo.Name}\"");
|
|
|
|
}
|
|
|
|
|
|
|
|
return argumentAttribute;
|
|
|
|
}
|
|
|
|
|
2019-07-02 03:39:22 +01:00
|
|
|
// For functions returning output values, the first registers
|
|
|
|
// are used to hold pointers where the value will be stored,
|
|
|
|
// so they can't be used to pass argument and we must
|
|
|
|
// skip them.
|
2018-12-18 05:33:36 +00:00
|
|
|
int byRefArgsCount = 0;
|
|
|
|
|
|
|
|
for (int index = 0; index < methodArgs.Length; index++)
|
|
|
|
{
|
|
|
|
if (methodArgs[index].ParameterType.IsByRef)
|
|
|
|
{
|
|
|
|
byRefArgsCount++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-09-20 00:59:48 +01:00
|
|
|
BindingFlags staticNonPublic = BindingFlags.NonPublic | BindingFlags.Static;
|
|
|
|
|
2019-07-02 03:39:22 +01:00
|
|
|
// Print all the arguments for debugging purposes.
|
2018-12-18 05:33:36 +00:00
|
|
|
int inputArgsCount = methodArgs.Length - byRefArgsCount;
|
|
|
|
|
2019-09-20 00:59:48 +01:00
|
|
|
if (inputArgsCount != 0)
|
|
|
|
{
|
|
|
|
generator.Emit(OpCodes.Ldc_I4, inputArgsCount);
|
2018-12-18 05:33:36 +00:00
|
|
|
|
2019-09-20 00:59:48 +01:00
|
|
|
generator.Emit(OpCodes.Newarr, typeof(object));
|
2018-12-18 05:33:36 +00:00
|
|
|
|
2019-09-20 00:59:48 +01:00
|
|
|
string argsFormat = svcName;
|
2018-12-18 05:33:36 +00:00
|
|
|
|
2020-01-13 02:04:28 +00:00
|
|
|
for (int index = 0; index < methodArgs.Length; index++)
|
2019-09-20 00:59:48 +01:00
|
|
|
{
|
2020-01-13 02:04:28 +00:00
|
|
|
Type argType = methodArgs[index].ParameterType;
|
|
|
|
|
|
|
|
// Ignore out argument for printing
|
|
|
|
if (argType.IsByRef)
|
|
|
|
{
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
RAttribute registerAttribute = GetRegisterAttribute(methodArgs[index]);
|
|
|
|
|
2019-09-20 00:59:48 +01:00
|
|
|
argsFormat += $" {methodArgs[index].Name}: 0x{{{index}:X8}},";
|
2018-12-18 05:33:36 +00:00
|
|
|
|
2019-09-20 00:59:48 +01:00
|
|
|
generator.Emit(OpCodes.Dup);
|
|
|
|
generator.Emit(OpCodes.Ldc_I4, index);
|
2018-12-18 05:33:36 +00:00
|
|
|
|
2019-09-20 00:59:48 +01:00
|
|
|
generator.Emit(OpCodes.Ldarg_1);
|
2020-01-13 02:04:28 +00:00
|
|
|
generator.Emit(OpCodes.Ldc_I4, registerAttribute.Index);
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 19:56:22 +01:00
|
|
|
|
2019-10-31 18:09:03 +00:00
|
|
|
MethodInfo info = typeof(ExecutionContext).GetMethod(nameof(ExecutionContext.GetX));
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 19:56:22 +01:00
|
|
|
|
2019-09-20 00:59:48 +01:00
|
|
|
generator.Emit(OpCodes.Call, info);
|
2018-12-18 05:33:36 +00:00
|
|
|
|
2019-09-20 00:59:48 +01:00
|
|
|
generator.Emit(OpCodes.Box, typeof(ulong));
|
2018-12-18 05:33:36 +00:00
|
|
|
|
2019-09-20 00:59:48 +01:00
|
|
|
generator.Emit(OpCodes.Stelem_Ref);
|
|
|
|
}
|
2018-12-18 05:33:36 +00:00
|
|
|
|
2019-09-20 00:59:48 +01:00
|
|
|
argsFormat = argsFormat.Substring(0, argsFormat.Length - 1);
|
2018-12-18 05:33:36 +00:00
|
|
|
|
2020-01-13 02:04:28 +00:00
|
|
|
generator.Emit(OpCodes.Ldstr, argsFormat);
|
2019-09-20 00:59:48 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
generator.Emit(OpCodes.Ldnull);
|
2018-12-18 05:33:36 +00:00
|
|
|
|
2019-09-20 00:59:48 +01:00
|
|
|
generator.Emit(OpCodes.Ldstr, svcName);
|
|
|
|
}
|
2018-12-18 05:33:36 +00:00
|
|
|
|
2020-05-04 04:41:29 +01:00
|
|
|
MethodInfo printArgsMethod = typeof(SyscallTable).GetMethod(nameof(PrintArguments), staticNonPublic);
|
2018-12-18 05:33:36 +00:00
|
|
|
|
|
|
|
generator.Emit(OpCodes.Call, printArgsMethod);
|
|
|
|
|
2019-07-02 03:39:22 +01:00
|
|
|
// Call the SVC function handler.
|
2018-12-18 05:33:36 +00:00
|
|
|
generator.Emit(OpCodes.Ldarg_0);
|
|
|
|
|
2020-01-13 02:04:28 +00:00
|
|
|
List<(LocalBuilder, RAttribute)> locals = new List<(LocalBuilder, RAttribute)>();
|
2018-12-18 05:33:36 +00:00
|
|
|
|
|
|
|
for (int index = 0; index < methodArgs.Length; index++)
|
|
|
|
{
|
|
|
|
Type argType = methodArgs[index].ParameterType;
|
2020-01-13 02:04:28 +00:00
|
|
|
RAttribute registerAttribute = GetRegisterAttribute(methodArgs[index]);
|
2018-12-18 05:33:36 +00:00
|
|
|
|
|
|
|
if (argType.IsByRef)
|
|
|
|
{
|
|
|
|
argType = argType.GetElementType();
|
|
|
|
|
|
|
|
LocalBuilder local = generator.DeclareLocal(argType);
|
|
|
|
|
2020-01-13 02:04:28 +00:00
|
|
|
locals.Add((local, registerAttribute));
|
2018-12-18 05:33:36 +00:00
|
|
|
|
|
|
|
if (!methodArgs[index].IsOut)
|
|
|
|
{
|
2019-10-25 00:34:35 +01:00
|
|
|
generator.Emit(OpCodes.Ldarg_1);
|
2020-01-13 02:04:28 +00:00
|
|
|
generator.Emit(OpCodes.Ldc_I4, registerAttribute.Index);
|
2019-10-25 00:34:35 +01:00
|
|
|
|
2019-10-31 18:09:03 +00:00
|
|
|
MethodInfo info = typeof(ExecutionContext).GetMethod(nameof(ExecutionContext.GetX));
|
2019-10-25 00:34:35 +01:00
|
|
|
|
|
|
|
generator.Emit(OpCodes.Call, info);
|
|
|
|
|
|
|
|
ConvertToArgType(argType);
|
|
|
|
|
|
|
|
generator.Emit(OpCodes.Stloc, local);
|
2018-12-18 05:33:36 +00:00
|
|
|
}
|
|
|
|
|
2019-09-20 00:59:48 +01:00
|
|
|
generator.Emit(OpCodes.Ldloca, local);
|
2018-12-18 05:33:36 +00:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
generator.Emit(OpCodes.Ldarg_1);
|
2020-01-13 02:04:28 +00:00
|
|
|
generator.Emit(OpCodes.Ldc_I4, registerAttribute.Index);
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 19:56:22 +01:00
|
|
|
|
2019-10-31 18:09:03 +00:00
|
|
|
MethodInfo info = typeof(ExecutionContext).GetMethod(nameof(ExecutionContext.GetX));
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 19:56:22 +01:00
|
|
|
|
|
|
|
generator.Emit(OpCodes.Call, info);
|
2018-12-18 05:33:36 +00:00
|
|
|
|
|
|
|
ConvertToArgType(argType);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
generator.Emit(OpCodes.Call, methodInfo);
|
|
|
|
|
|
|
|
Type retType = methodInfo.ReturnType;
|
|
|
|
|
2019-07-02 03:39:22 +01:00
|
|
|
// Print result code.
|
2018-12-18 05:33:36 +00:00
|
|
|
if (retType == typeof(KernelResult))
|
|
|
|
{
|
2020-05-04 04:41:29 +01:00
|
|
|
MethodInfo printResultMethod = typeof(SyscallTable).GetMethod(nameof(PrintResult), staticNonPublic);
|
2018-12-18 05:33:36 +00:00
|
|
|
|
|
|
|
generator.Emit(OpCodes.Dup);
|
|
|
|
generator.Emit(OpCodes.Ldstr, svcName);
|
|
|
|
generator.Emit(OpCodes.Call, printResultMethod);
|
|
|
|
}
|
|
|
|
|
2020-01-13 02:04:28 +00:00
|
|
|
uint registerInUse = 0;
|
|
|
|
|
2019-07-02 03:39:22 +01:00
|
|
|
// Save return value into register X0 (when the method has a return value).
|
2018-12-18 05:33:36 +00:00
|
|
|
if (retType != typeof(void))
|
|
|
|
{
|
|
|
|
CheckIfTypeIsSupported(retType, svcName);
|
|
|
|
|
|
|
|
LocalBuilder tempLocal = generator.DeclareLocal(retType);
|
|
|
|
|
|
|
|
generator.Emit(OpCodes.Stloc, tempLocal);
|
|
|
|
generator.Emit(OpCodes.Ldarg_1);
|
2020-01-13 02:04:28 +00:00
|
|
|
generator.Emit(OpCodes.Ldc_I4, 0);
|
2018-12-18 05:33:36 +00:00
|
|
|
generator.Emit(OpCodes.Ldloc, tempLocal);
|
|
|
|
|
|
|
|
ConvertToFieldType(retType);
|
|
|
|
|
2019-10-31 18:09:03 +00:00
|
|
|
MethodInfo info = typeof(ExecutionContext).GetMethod(nameof(ExecutionContext.SetX));
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 19:56:22 +01:00
|
|
|
|
|
|
|
generator.Emit(OpCodes.Call, info);
|
2020-01-13 02:04:28 +00:00
|
|
|
|
|
|
|
registerInUse |= 1u << 0;
|
2018-12-18 05:33:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
for (int index = 0; index < locals.Count; index++)
|
|
|
|
{
|
2020-01-13 02:04:28 +00:00
|
|
|
(LocalBuilder local, RAttribute attribute) = locals[index];
|
2020-01-19 22:21:53 +00:00
|
|
|
|
|
|
|
if ((registerInUse & (1u << attribute.Index)) != 0)
|
|
|
|
{
|
|
|
|
throw new InvalidSvcException($"Method \"{svcName}\" has conflicting output values at register index \"{attribute.Index}\".");
|
|
|
|
}
|
|
|
|
|
2018-12-18 05:33:36 +00:00
|
|
|
generator.Emit(OpCodes.Ldarg_1);
|
2020-01-13 02:04:28 +00:00
|
|
|
generator.Emit(OpCodes.Ldc_I4, attribute.Index);
|
|
|
|
generator.Emit(OpCodes.Ldloc, local);
|
2018-12-18 05:33:36 +00:00
|
|
|
|
2020-01-13 02:04:28 +00:00
|
|
|
ConvertToFieldType(local.LocalType);
|
2018-12-18 05:33:36 +00:00
|
|
|
|
2019-10-31 18:09:03 +00:00
|
|
|
MethodInfo info = typeof(ExecutionContext).GetMethod(nameof(ExecutionContext.SetX));
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 19:56:22 +01:00
|
|
|
|
|
|
|
generator.Emit(OpCodes.Call, info);
|
2020-01-13 02:04:28 +00:00
|
|
|
|
|
|
|
registerInUse |= 1u << attribute.Index;
|
2018-12-18 05:33:36 +00:00
|
|
|
}
|
|
|
|
|
2019-07-02 03:39:22 +01:00
|
|
|
// Zero out the remaining unused registers.
|
2020-01-13 02:04:28 +00:00
|
|
|
for (int i = 0; i < registerCleanCount; i++)
|
2018-12-18 05:33:36 +00:00
|
|
|
{
|
2020-01-13 02:04:28 +00:00
|
|
|
if ((registerInUse & (1u << i)) != 0)
|
|
|
|
{
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2018-12-18 05:33:36 +00:00
|
|
|
generator.Emit(OpCodes.Ldarg_1);
|
2020-01-13 02:04:28 +00:00
|
|
|
generator.Emit(OpCodes.Ldc_I4, i);
|
2018-12-18 05:33:36 +00:00
|
|
|
generator.Emit(OpCodes.Ldc_I8, 0L);
|
|
|
|
|
2019-10-31 18:09:03 +00:00
|
|
|
MethodInfo info = typeof(ExecutionContext).GetMethod(nameof(ExecutionContext.SetX));
|
2018-12-18 05:33:36 +00:00
|
|
|
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 19:56:22 +01:00
|
|
|
generator.Emit(OpCodes.Call, info);
|
2018-12-18 05:33:36 +00:00
|
|
|
}
|
|
|
|
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 19:56:22 +01:00
|
|
|
generator.Emit(OpCodes.Ret);
|
|
|
|
|
2022-02-13 13:50:07 +00:00
|
|
|
return method.CreateDelegate<Action<T, ExecutionContext>>();
|
2018-12-18 05:33:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
private static void CheckIfTypeIsSupported(Type type, string svcName)
|
|
|
|
{
|
|
|
|
switch (Type.GetTypeCode(type))
|
|
|
|
{
|
|
|
|
case TypeCode.UInt64:
|
|
|
|
case TypeCode.Int64:
|
|
|
|
case TypeCode.UInt32:
|
|
|
|
case TypeCode.Int32:
|
|
|
|
case TypeCode.UInt16:
|
|
|
|
case TypeCode.Int16:
|
|
|
|
case TypeCode.Byte:
|
|
|
|
case TypeCode.SByte:
|
|
|
|
case TypeCode.Boolean:
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
throw new InvalidSvcException($"Method \"{svcName}\" has a invalid ref type \"{type.Name}\".");
|
|
|
|
}
|
|
|
|
|
2019-09-20 00:59:48 +01:00
|
|
|
private static void PrintArguments(object[] argValues, string formatOrSvcName)
|
|
|
|
{
|
|
|
|
if (argValues != null)
|
|
|
|
{
|
2022-02-18 01:14:05 +00:00
|
|
|
Logger.Trace?.Print(LogClass.KernelSvc, string.Format(formatOrSvcName, argValues));
|
2019-09-20 00:59:48 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2022-02-18 01:14:05 +00:00
|
|
|
Logger.Trace?.Print(LogClass.KernelSvc, formatOrSvcName);
|
2019-09-20 00:59:48 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-12-18 05:33:36 +00:00
|
|
|
private static void PrintResult(KernelResult result, string svcName)
|
|
|
|
{
|
2021-12-23 17:43:30 +00:00
|
|
|
if (result != KernelResult.Success &&
|
|
|
|
result != KernelResult.TimedOut &&
|
2018-12-18 05:33:36 +00:00
|
|
|
result != KernelResult.Cancelled &&
|
2021-12-23 17:43:30 +00:00
|
|
|
result != KernelResult.PortRemoteClosed &&
|
2018-12-18 05:33:36 +00:00
|
|
|
result != KernelResult.InvalidState)
|
|
|
|
{
|
2020-08-04 00:32:53 +01:00
|
|
|
Logger.Warning?.Print(LogClass.KernelSvc, $"{svcName} returned error {result}.");
|
2018-12-18 05:33:36 +00:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2022-02-18 00:08:07 +00:00
|
|
|
Logger.Trace?.Print(LogClass.KernelSvc, $"{svcName} returned result {result}.");
|
2018-12-18 05:33:36 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2019-09-20 00:59:48 +01:00
|
|
|
}
|