2020-03-10 05:17:30 +00:00
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namespace ARMeilleure.Decoders
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{
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class OpCode32SimdLong : OpCode32SimdBase
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{
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2020-10-21 13:13:44 +01:00
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public bool U { get; }
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdLong(inst, address, opCode);
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2020-03-10 05:17:30 +00:00
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public OpCode32SimdLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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int imm3h = (opCode >> 19) & 0x7;
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// The value must be a power of 2, otherwise it is the encoding of another instruction.
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switch (imm3h)
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{
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case 1: Size = 0; break;
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case 2: Size = 1; break;
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case 4: Size = 2; break;
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}
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U = ((opCode >> 24) & 0x1) != 0;
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RegisterSize = RegisterSize.Simd64;
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Vd = ((opCode >> 18) & 0x10) | ((opCode >> 12) & 0xf);
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Vm = ((opCode >> 1) & 0x10) | ((opCode >> 0) & 0xf);
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}
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}
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}
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