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Implement fast path for AES crypto instructions on Arm64 (#5281)
* Implement fast path for AES crypto instructions on Arm64 * PPTC version bump * Use AES HW feature check
This commit is contained in:
parent
eb0bb36bbf
commit
193ca3c9a2
9 changed files with 79 additions and 16 deletions
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@ -168,8 +168,6 @@ namespace ARMeilleure.CodeGen.Arm64
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Logger.StartPass(PassName.CodeGeneration);
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Logger.StartPass(PassName.CodeGeneration);
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//Console.Error.WriteLine(IRDumper.GetDump(cfg));
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bool relocatable = (cctx.Options & CompilerOptions.Relocatable) != 0;
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bool relocatable = (cctx.Options & CompilerOptions.Relocatable) != 0;
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CodeGenContext context = new(allocResult, maxCallArgs, cfg.Blocks.Count, relocatable);
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CodeGenContext context = new(allocResult, maxCallArgs, cfg.Blocks.Count, relocatable);
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@ -179,6 +179,35 @@ namespace ARMeilleure.CodeGen.Arm64
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(uint)operation.GetSource(2).AsInt32());
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(uint)operation.GetSource(2).AsInt32());
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break;
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break;
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case IntrinsicType.Vector128Unary:
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GenerateVectorUnary(
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context,
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1,
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0,
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info.Inst,
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operation.Destination,
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operation.GetSource(0));
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break;
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case IntrinsicType.Vector128Binary:
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GenerateVectorBinary(
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context,
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1,
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0,
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info.Inst,
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operation.Destination,
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operation.GetSource(0),
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operation.GetSource(1));
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break;
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case IntrinsicType.Vector128BinaryRd:
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GenerateVectorUnary(
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context,
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1,
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0,
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info.Inst,
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operation.Destination,
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operation.GetSource(1));
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break;
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case IntrinsicType.VectorUnary:
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case IntrinsicType.VectorUnary:
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GenerateVectorUnary(
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GenerateVectorUnary(
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context,
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context,
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@ -19,8 +19,8 @@ namespace ARMeilleure.CodeGen.Arm64
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Add(Intrinsic.Arm64AddvV, new IntrinsicInfo(0x0e31b800u, IntrinsicType.VectorUnary));
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Add(Intrinsic.Arm64AddvV, new IntrinsicInfo(0x0e31b800u, IntrinsicType.VectorUnary));
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Add(Intrinsic.Arm64AddS, new IntrinsicInfo(0x5e208400u, IntrinsicType.ScalarBinary));
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Add(Intrinsic.Arm64AddS, new IntrinsicInfo(0x5e208400u, IntrinsicType.ScalarBinary));
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Add(Intrinsic.Arm64AddV, new IntrinsicInfo(0x0e208400u, IntrinsicType.VectorBinary));
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Add(Intrinsic.Arm64AddV, new IntrinsicInfo(0x0e208400u, IntrinsicType.VectorBinary));
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Add(Intrinsic.Arm64AesdV, new IntrinsicInfo(0x4e285800u, IntrinsicType.Vector128Unary));
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Add(Intrinsic.Arm64AesdV, new IntrinsicInfo(0x4e285800u, IntrinsicType.Vector128BinaryRd));
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Add(Intrinsic.Arm64AeseV, new IntrinsicInfo(0x4e284800u, IntrinsicType.Vector128Unary));
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Add(Intrinsic.Arm64AeseV, new IntrinsicInfo(0x4e284800u, IntrinsicType.Vector128BinaryRd));
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Add(Intrinsic.Arm64AesimcV, new IntrinsicInfo(0x4e287800u, IntrinsicType.Vector128Unary));
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Add(Intrinsic.Arm64AesimcV, new IntrinsicInfo(0x4e287800u, IntrinsicType.Vector128Unary));
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Add(Intrinsic.Arm64AesmcV, new IntrinsicInfo(0x4e286800u, IntrinsicType.Vector128Unary));
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Add(Intrinsic.Arm64AesmcV, new IntrinsicInfo(0x4e286800u, IntrinsicType.Vector128Unary));
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Add(Intrinsic.Arm64AndV, new IntrinsicInfo(0x0e201c00u, IntrinsicType.VectorBinaryBitwise));
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Add(Intrinsic.Arm64AndV, new IntrinsicInfo(0x0e201c00u, IntrinsicType.VectorBinaryBitwise));
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@ -23,6 +23,10 @@ namespace ARMeilleure.CodeGen.Arm64
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ScalarTernaryShlRd,
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ScalarTernaryShlRd,
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ScalarTernaryShrRd,
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ScalarTernaryShrRd,
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Vector128Unary,
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Vector128Binary,
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Vector128BinaryRd,
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VectorUnary,
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VectorUnary,
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VectorUnaryBitwise,
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VectorUnaryBitwise,
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VectorUnaryByElem,
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VectorUnaryByElem,
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@ -50,9 +54,6 @@ namespace ARMeilleure.CodeGen.Arm64
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VectorTernaryShlRd,
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VectorTernaryShlRd,
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VectorTernaryShrRd,
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VectorTernaryShrRd,
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Vector128Unary,
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Vector128Binary,
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GetRegister,
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GetRegister,
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SetRegister
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SetRegister
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}
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}
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@ -746,6 +746,7 @@ namespace ARMeilleure.CodeGen.Arm64
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info.Type == IntrinsicType.ScalarTernaryFPRdByElem ||
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info.Type == IntrinsicType.ScalarTernaryFPRdByElem ||
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info.Type == IntrinsicType.ScalarTernaryShlRd ||
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info.Type == IntrinsicType.ScalarTernaryShlRd ||
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info.Type == IntrinsicType.ScalarTernaryShrRd ||
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info.Type == IntrinsicType.ScalarTernaryShrRd ||
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info.Type == IntrinsicType.Vector128BinaryRd ||
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info.Type == IntrinsicType.VectorBinaryRd ||
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info.Type == IntrinsicType.VectorBinaryRd ||
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info.Type == IntrinsicType.VectorInsertByElem ||
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info.Type == IntrinsicType.VectorInsertByElem ||
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info.Type == IntrinsicType.VectorTernaryRd ||
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info.Type == IntrinsicType.VectorTernaryRd ||
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@ -17,7 +17,11 @@ namespace ARMeilleure.Instructions
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Operand res;
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Operand res;
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if (Optimizations.UseAesni)
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if (Optimizations.UseArm64Aes)
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{
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res = context.AddIntrinsic(Intrinsic.Arm64AesdV, d, n);
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}
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else if (Optimizations.UseAesni)
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{
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{
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res = context.AddIntrinsic(Intrinsic.X86Aesdeclast, context.AddIntrinsic(Intrinsic.X86Xorpd, d, n), context.VectorZero());
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res = context.AddIntrinsic(Intrinsic.X86Aesdeclast, context.AddIntrinsic(Intrinsic.X86Xorpd, d, n), context.VectorZero());
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}
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}
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@ -38,7 +42,11 @@ namespace ARMeilleure.Instructions
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Operand res;
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Operand res;
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if (Optimizations.UseAesni)
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if (Optimizations.UseArm64Aes)
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{
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res = context.AddIntrinsic(Intrinsic.Arm64AeseV, d, n);
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}
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else if (Optimizations.UseAesni)
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{
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{
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res = context.AddIntrinsic(Intrinsic.X86Aesenclast, context.AddIntrinsic(Intrinsic.X86Xorpd, d, n), context.VectorZero());
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res = context.AddIntrinsic(Intrinsic.X86Aesenclast, context.AddIntrinsic(Intrinsic.X86Xorpd, d, n), context.VectorZero());
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}
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}
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@ -58,7 +66,11 @@ namespace ARMeilleure.Instructions
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Operand res;
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Operand res;
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if (Optimizations.UseAesni)
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if (Optimizations.UseArm64Aes)
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{
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res = context.AddIntrinsic(Intrinsic.Arm64AesimcV, n);
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}
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else if (Optimizations.UseAesni)
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{
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{
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res = context.AddIntrinsic(Intrinsic.X86Aesimc, n);
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res = context.AddIntrinsic(Intrinsic.X86Aesimc, n);
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}
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}
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@ -78,7 +90,11 @@ namespace ARMeilleure.Instructions
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Operand res;
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Operand res;
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if (Optimizations.UseAesni)
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if (Optimizations.UseArm64Aes)
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{
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res = context.AddIntrinsic(Intrinsic.Arm64AesmcV, n);
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}
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else if (Optimizations.UseAesni)
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{
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{
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Operand roundKey = context.VectorZero();
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Operand roundKey = context.VectorZero();
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@ -17,7 +17,11 @@ namespace ARMeilleure.Instructions
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Operand res;
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Operand res;
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if (Optimizations.UseAesni)
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if (Optimizations.UseArm64Aes)
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{
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res = context.AddIntrinsic(Intrinsic.Arm64AesdV, d, n);
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}
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else if (Optimizations.UseAesni)
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{
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{
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res = context.AddIntrinsic(Intrinsic.X86Aesdeclast, context.AddIntrinsic(Intrinsic.X86Xorpd, d, n), context.VectorZero());
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res = context.AddIntrinsic(Intrinsic.X86Aesdeclast, context.AddIntrinsic(Intrinsic.X86Xorpd, d, n), context.VectorZero());
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}
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}
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@ -38,7 +42,11 @@ namespace ARMeilleure.Instructions
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Operand res;
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Operand res;
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if (Optimizations.UseAesni)
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if (Optimizations.UseArm64Aes)
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{
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res = context.AddIntrinsic(Intrinsic.Arm64AeseV, d, n);
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}
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else if (Optimizations.UseAesni)
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{
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{
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res = context.AddIntrinsic(Intrinsic.X86Aesenclast, context.AddIntrinsic(Intrinsic.X86Xorpd, d, n), context.VectorZero());
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res = context.AddIntrinsic(Intrinsic.X86Aesenclast, context.AddIntrinsic(Intrinsic.X86Xorpd, d, n), context.VectorZero());
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}
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}
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@ -58,7 +66,11 @@ namespace ARMeilleure.Instructions
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Operand res;
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Operand res;
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if (Optimizations.UseAesni)
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if (Optimizations.UseArm64Aes)
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{
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res = context.AddIntrinsic(Intrinsic.Arm64AesimcV, n);
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}
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else if (Optimizations.UseAesni)
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{
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{
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res = context.AddIntrinsic(Intrinsic.X86Aesimc, n);
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res = context.AddIntrinsic(Intrinsic.X86Aesimc, n);
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}
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}
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@ -78,7 +90,11 @@ namespace ARMeilleure.Instructions
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Operand res;
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Operand res;
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if (Optimizations.UseAesni)
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if (Optimizations.UseArm64Aes)
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{
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res = context.AddIntrinsic(Intrinsic.Arm64AesmcV, n);
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}
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else if (Optimizations.UseAesni)
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{
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{
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Operand roundKey = context.VectorZero();
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Operand roundKey = context.VectorZero();
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@ -13,6 +13,7 @@ namespace ARMeilleure
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public static bool UseUnmanagedDispatchLoop { get; set; } = true;
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public static bool UseUnmanagedDispatchLoop { get; set; } = true;
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public static bool UseAdvSimdIfAvailable { get; set; } = true;
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public static bool UseAdvSimdIfAvailable { get; set; } = true;
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public static bool UseArm64AesIfAvailable { get; set; } = true;
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public static bool UseArm64PmullIfAvailable { get; set; } = true;
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public static bool UseArm64PmullIfAvailable { get; set; } = true;
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public static bool UseSseIfAvailable { get; set; } = true;
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public static bool UseSseIfAvailable { get; set; } = true;
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@ -41,6 +42,7 @@ namespace ARMeilleure
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}
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}
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internal static bool UseAdvSimd => UseAdvSimdIfAvailable && Arm64HardwareCapabilities.SupportsAdvSimd;
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internal static bool UseAdvSimd => UseAdvSimdIfAvailable && Arm64HardwareCapabilities.SupportsAdvSimd;
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internal static bool UseArm64Aes => UseArm64AesIfAvailable && Arm64HardwareCapabilities.SupportsAes;
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internal static bool UseArm64Pmull => UseArm64PmullIfAvailable && Arm64HardwareCapabilities.SupportsPmull;
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internal static bool UseArm64Pmull => UseArm64PmullIfAvailable && Arm64HardwareCapabilities.SupportsPmull;
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internal static bool UseSse => UseSseIfAvailable && X86HardwareCapabilities.SupportsSse;
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internal static bool UseSse => UseSseIfAvailable && X86HardwareCapabilities.SupportsSse;
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@ -30,7 +30,7 @@ namespace ARMeilleure.Translation.PTC
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private const string OuterHeaderMagicString = "PTCohd\0\0";
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private const string OuterHeaderMagicString = "PTCohd\0\0";
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private const string InnerHeaderMagicString = "PTCihd\0\0";
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private const string InnerHeaderMagicString = "PTCihd\0\0";
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private const uint InternalVersion = 4661; //! To be incremented manually for each change to the ARMeilleure project.
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private const uint InternalVersion = 5281; //! To be incremented manually for each change to the ARMeilleure project.
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private const string ActualDir = "0";
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private const string ActualDir = "0";
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private const string BackupDir = "1";
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private const string BackupDir = "1";
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