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Update CpuTestMisc.cs
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1 changed files with 120 additions and 2 deletions
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@ -1,3 +1,5 @@
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#define Misc
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using ChocolArm64.State;
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using ChocolArm64.State;
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using NUnit.Framework;
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using NUnit.Framework;
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@ -6,9 +8,120 @@ using System.Runtime.Intrinsics.X86;
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namespace Ryujinx.Tests.Cpu
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namespace Ryujinx.Tests.Cpu
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{
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{
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[Category("Misc"), Explicit]
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[Category("Misc")]
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public sealed class CpuTestMisc : CpuTest
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public sealed class CpuTestMisc : CpuTest
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{
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{
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#if Misc
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private const int RndCnt = 2;
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private const int RndCntImm = 2;
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#region "AluImm & Csel"
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[Test, Pairwise]
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public void Adds_Csinc_64bit([Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
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[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
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[Values(0b00u, 0b01u)] uint shift, // <LSL #0, LSL #12>
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[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
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0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
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0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
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0b1100u, 0b1101u)] uint cond) // GT, LE>
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{
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uint opCmn = 0xB100001F; // ADDS X31, X0, #0, LSL #0 -> CMN X0, #0, LSL #0
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uint opCset = 0x9A9F07E0; // CSINC X0, X31, X31, EQ -> CSET X0, NE
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opCmn |= ((shift & 3) << 22) | ((imm & 4095) << 10);
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opCset |= ((cond & 15) << 12);
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SetThreadState(x0: xn);
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Opcode(opCmn);
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Opcode(opCset);
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Opcode(0xD4200000); // BRK #0
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Opcode(0xD65F03C0); // RET
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ExecuteOpcodes();
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Adds_Csinc_32bit([Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
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[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
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[Values(0b00u, 0b01u)] uint shift, // <LSL #0, LSL #12>
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[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
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0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
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0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
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0b1100u, 0b1101u)] uint cond) // GT, LE>
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{
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uint opCmn = 0x3100001F; // ADDS W31, W0, #0, LSL #0 -> CMN W0, #0, LSL #0
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uint opCset = 0x1A9F07E0; // CSINC W0, W31, W31, EQ -> CSET W0, NE
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opCmn |= ((shift & 3) << 22) | ((imm & 4095) << 10);
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opCset |= ((cond & 15) << 12);
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SetThreadState(x0: wn);
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Opcode(opCmn);
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Opcode(opCset);
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Opcode(0xD4200000); // BRK #0
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Opcode(0xD65F03C0); // RET
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ExecuteOpcodes();
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Subs_Csinc_64bit([Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
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[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
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[Values(0b00u, 0b01u)] uint shift, // <LSL #0, LSL #12>
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[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
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0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
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0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
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0b1100u, 0b1101u)] uint cond) // GT, LE>
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{
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uint opCmp = 0xF100001F; // SUBS X31, X0, #0, LSL #0 -> CMP X0, #0, LSL #0
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uint opCset = 0x9A9F07E0; // CSINC X0, X31, X31, EQ -> CSET X0, NE
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opCmp |= ((shift & 3) << 22) | ((imm & 4095) << 10);
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opCset |= ((cond & 15) << 12);
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SetThreadState(x0: xn);
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Opcode(opCmp);
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Opcode(opCset);
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Opcode(0xD4200000); // BRK #0
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Opcode(0xD65F03C0); // RET
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ExecuteOpcodes();
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Subs_Csinc_32bit([Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
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[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
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[Values(0b00u, 0b01u)] uint shift, // <LSL #0, LSL #12>
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[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
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0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
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0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
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0b1100u, 0b1101u)] uint cond) // GT, LE>
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{
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uint opCmp = 0x7100001F; // SUBS W31, W0, #0, LSL #0 -> CMP W0, #0, LSL #0
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uint opCset = 0x1A9F07E0; // CSINC W0, W31, W31, EQ -> CSET W0, NE
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opCmp |= ((shift & 3) << 22) | ((imm & 4095) << 10);
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opCset |= ((cond & 15) << 12);
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SetThreadState(x0: wn);
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Opcode(opCmp);
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Opcode(opCset);
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Opcode(0xD4200000); // BRK #0
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Opcode(0xD65F03C0); // RET
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ExecuteOpcodes();
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CompareAgainstUnicorn();
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}
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#endregion
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[Explicit]
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[TestCase(0xFFFFFFFDu)] // Roots.
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[TestCase(0xFFFFFFFDu)] // Roots.
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[TestCase(0x00000005u)]
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[TestCase(0x00000005u)]
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public void Misc1(uint a)
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public void Misc1(uint a)
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@ -42,6 +155,7 @@ namespace Ryujinx.Tests.Cpu
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Assert.That(GetThreadState().X0, Is.Zero);
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Assert.That(GetThreadState().X0, Is.Zero);
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}
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}
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[Explicit]
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[TestCase(-20f, -5f)] // 18 integer solutions.
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[TestCase(-20f, -5f)] // 18 integer solutions.
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[TestCase(-12f, -6f)]
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[TestCase(-12f, -6f)]
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[TestCase(-12f, 3f)]
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[TestCase(-12f, 3f)]
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@ -91,6 +205,7 @@ namespace Ryujinx.Tests.Cpu
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Assert.That(Sse41.Extract(GetThreadState().V0, (byte)0), Is.EqualTo(16f));
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Assert.That(Sse41.Extract(GetThreadState().V0, (byte)0), Is.EqualTo(16f));
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}
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}
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[Explicit]
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[TestCase(-20d, -5d)] // 18 integer solutions.
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[TestCase(-20d, -5d)] // 18 integer solutions.
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[TestCase(-12d, -6d)]
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[TestCase(-12d, -6d)]
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[TestCase(-12d, 3d)]
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[TestCase(-12d, 3d)]
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@ -140,7 +255,7 @@ namespace Ryujinx.Tests.Cpu
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Assert.That(VectorExtractDouble(GetThreadState().V0, (byte)0), Is.EqualTo(16d));
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Assert.That(VectorExtractDouble(GetThreadState().V0, (byte)0), Is.EqualTo(16d));
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}
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}
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[Test]
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[Test, Ignore("The Tester supports only one return point.")]
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public void MiscF([Range(0u, 92u, 1u)] uint a)
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public void MiscF([Range(0u, 92u, 1u)] uint a)
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{
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{
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ulong Fn(uint n)
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ulong Fn(uint n)
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@ -213,6 +328,7 @@ namespace Ryujinx.Tests.Cpu
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Assert.That(GetThreadState().X0, Is.EqualTo(Fn(a)));
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Assert.That(GetThreadState().X0, Is.EqualTo(Fn(a)));
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}
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}
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[Explicit]
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[Test]
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[Test]
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public void MiscR()
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public void MiscR()
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{
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{
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@ -255,6 +371,7 @@ namespace Ryujinx.Tests.Cpu
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Assert.That(GetThreadState().X0, Is.EqualTo(result));
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Assert.That(GetThreadState().X0, Is.EqualTo(result));
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}
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}
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[Explicit]
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[TestCase( 0ul)]
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[TestCase( 0ul)]
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[TestCase( 1ul)]
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[TestCase( 1ul)]
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[TestCase( 2ul)]
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[TestCase( 2ul)]
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@ -266,5 +383,6 @@ namespace Ryujinx.Tests.Cpu
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Assert.That(threadState.X0, Is.EqualTo(a));
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Assert.That(threadState.X0, Is.EqualTo(a));
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}
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}
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#endif
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}
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}
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}
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}
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