mirrors/Ryujinx
1
0
Fork 0
mirror of https://github.com/Ryujinx/Ryujinx.git synced 2024-12-18 09:52:02 +00:00
Code Issues Releases Activity

Fix REV64 (vector) instruction

Browse source
This commit is contained in:
gdkchan 2018-03-02 20:24:16 -03:00
parent 829b1b1cc0
commit efef605b26
3 changed files with 22 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
ChocolArm64/AOpCodeTable.cs
View file

@ -230,7 +230,7 @@ namespace ChocolArm64
Set("0x10111000100000010110xxxxxxxxxx", AInstEmit.Not_V, typeof(AOpCodeSimd)); Set("0x10111000100000010110xxxxxxxxxx", AInstEmit.Not_V, typeof(AOpCodeSimd));
Set("0x001110101xxxxx000111xxxxxxxxxx", AInstEmit.Orr_V, typeof(AOpCodeSimdReg)); Set("0x001110101xxxxx000111xxxxxxxxxx", AInstEmit.Orr_V, typeof(AOpCodeSimdReg));
Set("0x00111100000xxx<<x101xxxxxxxxxx", AInstEmit.Orr_Vi, typeof(AOpCodeSimdImm)); Set("0x00111100000xxx<<x101xxxxxxxxxx", AInstEmit.Orr_Vi, typeof(AOpCodeSimdImm));
Set("0x001110xx100000000010xxxxxxxxxx", AInstEmit.Rev64_V, typeof(AOpCodeSimd)); Set("0x001110<<100000000010xxxxxxxxxx", AInstEmit.Rev64_V, typeof(AOpCodeSimd));
Set("0x001110<<1xxxxx000100xxxxxxxxxx", AInstEmit.Saddw_V, typeof(AOpCodeSimdReg)); Set("0x001110<<1xxxxx000100xxxxxxxxxx", AInstEmit.Saddw_V, typeof(AOpCodeSimdReg));
Set("x0011110xx100010000000xxxxxxxxxx", AInstEmit.Scvtf_Gp, typeof(AOpCodeSimdCvt)); Set("x0011110xx100010000000xxxxxxxxxx", AInstEmit.Scvtf_Gp, typeof(AOpCodeSimdCvt));
Set("010111100x100001110110xxxxxxxxxx", AInstEmit.Scvtf_S, typeof(AOpCodeSimd)); Set("010111100x100001110110xxxxxxxxxx", AInstEmit.Scvtf_S, typeof(AOpCodeSimd));

26
ChocolArm64/Instruction/AInstEmitSimdLogical.cs
View file

@ -1,5 +1,6 @@
using ChocolArm64.Decoder;
using ChocolArm64.State;
using ChocolArm64.Translation; using ChocolArm64.Translation;
using System;
using System.Reflection.Emit; using System.Reflection.Emit;
using static ChocolArm64.Instruction.AInstEmitSimdHelper; using static ChocolArm64.Instruction.AInstEmitSimdHelper;
@ -69,12 +70,25 @@ namespace ChocolArm64.Instruction
public static void Rev64_V(AILEmitterCtx Context) public static void Rev64_V(AILEmitterCtx Context)
{ {
Action Emit = () => AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
int Bytes = Context.CurrOp.GetBitsCount() >> 3;
int Elems = Bytes >> Op.Size;
int RevIndex = Elems - 1;
for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
{ {
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.ReverseBits64)); EmitVectorExtractZx(Context, Op.Rn, RevIndex--, Op.Size);
};
EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
EmitVectorUnaryOpZx(Context, Emit); }
if (Op.RegisterSize == ARegisterSize.SIMD64)
{
EmitVectorZeroUpper(Context, Op.Rd);
}
} }
} }
} }

2
ChocolArm64/Instruction/ASoftFallback.cs
View file

@ -75,7 +75,7 @@ namespace ChocolArm64.Instruction
private static ulong ReverseBytes(ulong Value, RevSize Size) private static ulong ReverseBytes(ulong Value, RevSize Size)
{ {
Value = ((Value & 0xff00ff00ff00ff00) >> 8) | ((Value & 0x00ff00ff00ff00ff) << 8); Value = ((Value & 0xff00ff00ff00ff00) >> 8) | ((Value & 0x00ff00ff00ff00ff) << 8);
if (Size == RevSize.Rev16) if (Size == RevSize.Rev16)
{ {